Loading arch/arm/mach-msm/board-samarium.c +1 −1 Original line number Diff line number Diff line Loading @@ -148,5 +148,5 @@ DT_MACHINE_START(MSMSAMARIUM_DT, "Qualcomm MSM Samarium(Flattened Device Tree)") .reserve = msmsamarium_reserve, .init_very_early = msmsamarium_init_very_early, .restart = msm_restart, .smp = &msm8974_smp_ops, .smp = &msm8962_smp_ops, MACHINE_END arch/arm/mach-msm/platsmp.c +60 −4 Original line number Diff line number Diff line Loading @@ -35,6 +35,9 @@ #define SCSS_CPU1CORE_RESET 0xD80 #define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64 #define MSM8960_SAW2_BASE_ADDR 0x02089000 #define MSM8962_SAW2_BASE_ADDR 0xF9089000 #define APCS_ALIAS0_BASE_ADDR 0xF9088000 /* * Write pen_release in a way that is guaranteed to be visible to all * observers, irrespective of whether they're taking part in coherency Loading Loading @@ -156,6 +159,33 @@ static int __cpuinit msm8974_release_secondary(unsigned long base, return 0; } static int __cpuinit msm8962_release_secondary(unsigned long base, unsigned int cpu) { void *base_ptr = ioremap_nocache(base + (cpu * 0x10000), SZ_4K); if (!base_ptr) return -ENODEV; msm_spm_turn_on_cpu_rail(MSM8962_SAW2_BASE_ADDR, cpu); writel_relaxed(0x021, base_ptr+0x04); mb(); udelay(2); writel_relaxed(0x020, base_ptr+0x04); mb(); udelay(2); writel_relaxed(0x000, base_ptr+0x04); mb(); writel_relaxed(0x080, base_ptr+0x04); mb(); iounmap(base_ptr); return 0; } static int __cpuinit arm_release_secondary(unsigned long base, unsigned int cpu) { void *base_ptr = ioremap_nocache(base + (cpu * 0x10000), SZ_4K); Loading Loading @@ -270,9 +300,24 @@ int __cpuinit msm8974_boot_secondary(unsigned int cpu, struct task_struct *idle) if (per_cpu(cold_boot_done, cpu) == false) { if (of_board_is_sim()) release_secondary_sim(0xf9088000, cpu); release_secondary_sim(APCS_ALIAS0_BASE_ADDR, cpu); else if (!of_board_is_rumi()) msm8974_release_secondary(0xf9088000, cpu); msm8974_release_secondary(APCS_ALIAS0_BASE_ADDR, cpu); per_cpu(cold_boot_done, cpu) = true; } return release_from_pen(cpu); } int __cpuinit msm8962_boot_secondary(unsigned int cpu, struct task_struct *idle) { pr_debug("Starting secondary CPU %d\n", cpu); if (per_cpu(cold_boot_done, cpu) == false) { if (of_board_is_sim()) release_secondary_sim(APCS_ALIAS0_BASE_ADDR, cpu); else if (!of_board_is_rumi()) msm8962_release_secondary(APCS_ALIAS0_BASE_ADDR, cpu); per_cpu(cold_boot_done, cpu) = true; } Loading @@ -285,9 +330,9 @@ int __cpuinit arm_boot_secondary(unsigned int cpu, struct task_struct *idle) if (per_cpu(cold_boot_done, cpu) == false) { if (of_board_is_sim()) release_secondary_sim(0xf9088000, cpu); release_secondary_sim(APCS_ALIAS0_BASE_ADDR, cpu); else if (!of_board_is_rumi()) arm_release_secondary(0xf9088000, cpu); arm_release_secondary(APCS_ALIAS0_BASE_ADDR, cpu); per_cpu(cold_boot_done, cpu) = true; } Loading Loading @@ -376,6 +421,17 @@ struct smp_operations msm8974_smp_ops __initdata = { #endif }; struct smp_operations msm8962_smp_ops __initdata = { .smp_init_cpus = msm_smp_init_cpus, .smp_prepare_cpus = msm_platform_smp_prepare_cpus, .smp_secondary_init = msm_secondary_init, .smp_boot_secondary = msm8962_boot_secondary, #ifdef CONFIG_HOTPLUG .cpu_die = msm_cpu_die, .cpu_kill = msm_cpu_kill, #endif }; struct smp_operations msm8960_smp_ops __initdata = { .smp_init_cpus = msm_smp_init_cpus, .smp_prepare_cpus = msm_platform_smp_prepare_cpus, Loading arch/arm/mach-msm/platsmp.h +2 −1 Original line number Diff line number Diff line /* Copyright (c) 2012, The Linux Foundation. All rights reserved. /* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading @@ -19,5 +19,6 @@ int msm_cpu_kill(unsigned int cpu); extern struct smp_operations arm_smp_ops; extern struct smp_operations msm8960_smp_ops; extern struct smp_operations msm8974_smp_ops; extern struct smp_operations msm8962_smp_ops; extern struct smp_operations msm8625_smp_ops; extern struct smp_operations scorpion_smp_ops; Loading
arch/arm/mach-msm/board-samarium.c +1 −1 Original line number Diff line number Diff line Loading @@ -148,5 +148,5 @@ DT_MACHINE_START(MSMSAMARIUM_DT, "Qualcomm MSM Samarium(Flattened Device Tree)") .reserve = msmsamarium_reserve, .init_very_early = msmsamarium_init_very_early, .restart = msm_restart, .smp = &msm8974_smp_ops, .smp = &msm8962_smp_ops, MACHINE_END
arch/arm/mach-msm/platsmp.c +60 −4 Original line number Diff line number Diff line Loading @@ -35,6 +35,9 @@ #define SCSS_CPU1CORE_RESET 0xD80 #define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64 #define MSM8960_SAW2_BASE_ADDR 0x02089000 #define MSM8962_SAW2_BASE_ADDR 0xF9089000 #define APCS_ALIAS0_BASE_ADDR 0xF9088000 /* * Write pen_release in a way that is guaranteed to be visible to all * observers, irrespective of whether they're taking part in coherency Loading Loading @@ -156,6 +159,33 @@ static int __cpuinit msm8974_release_secondary(unsigned long base, return 0; } static int __cpuinit msm8962_release_secondary(unsigned long base, unsigned int cpu) { void *base_ptr = ioremap_nocache(base + (cpu * 0x10000), SZ_4K); if (!base_ptr) return -ENODEV; msm_spm_turn_on_cpu_rail(MSM8962_SAW2_BASE_ADDR, cpu); writel_relaxed(0x021, base_ptr+0x04); mb(); udelay(2); writel_relaxed(0x020, base_ptr+0x04); mb(); udelay(2); writel_relaxed(0x000, base_ptr+0x04); mb(); writel_relaxed(0x080, base_ptr+0x04); mb(); iounmap(base_ptr); return 0; } static int __cpuinit arm_release_secondary(unsigned long base, unsigned int cpu) { void *base_ptr = ioremap_nocache(base + (cpu * 0x10000), SZ_4K); Loading Loading @@ -270,9 +300,24 @@ int __cpuinit msm8974_boot_secondary(unsigned int cpu, struct task_struct *idle) if (per_cpu(cold_boot_done, cpu) == false) { if (of_board_is_sim()) release_secondary_sim(0xf9088000, cpu); release_secondary_sim(APCS_ALIAS0_BASE_ADDR, cpu); else if (!of_board_is_rumi()) msm8974_release_secondary(0xf9088000, cpu); msm8974_release_secondary(APCS_ALIAS0_BASE_ADDR, cpu); per_cpu(cold_boot_done, cpu) = true; } return release_from_pen(cpu); } int __cpuinit msm8962_boot_secondary(unsigned int cpu, struct task_struct *idle) { pr_debug("Starting secondary CPU %d\n", cpu); if (per_cpu(cold_boot_done, cpu) == false) { if (of_board_is_sim()) release_secondary_sim(APCS_ALIAS0_BASE_ADDR, cpu); else if (!of_board_is_rumi()) msm8962_release_secondary(APCS_ALIAS0_BASE_ADDR, cpu); per_cpu(cold_boot_done, cpu) = true; } Loading @@ -285,9 +330,9 @@ int __cpuinit arm_boot_secondary(unsigned int cpu, struct task_struct *idle) if (per_cpu(cold_boot_done, cpu) == false) { if (of_board_is_sim()) release_secondary_sim(0xf9088000, cpu); release_secondary_sim(APCS_ALIAS0_BASE_ADDR, cpu); else if (!of_board_is_rumi()) arm_release_secondary(0xf9088000, cpu); arm_release_secondary(APCS_ALIAS0_BASE_ADDR, cpu); per_cpu(cold_boot_done, cpu) = true; } Loading Loading @@ -376,6 +421,17 @@ struct smp_operations msm8974_smp_ops __initdata = { #endif }; struct smp_operations msm8962_smp_ops __initdata = { .smp_init_cpus = msm_smp_init_cpus, .smp_prepare_cpus = msm_platform_smp_prepare_cpus, .smp_secondary_init = msm_secondary_init, .smp_boot_secondary = msm8962_boot_secondary, #ifdef CONFIG_HOTPLUG .cpu_die = msm_cpu_die, .cpu_kill = msm_cpu_kill, #endif }; struct smp_operations msm8960_smp_ops __initdata = { .smp_init_cpus = msm_smp_init_cpus, .smp_prepare_cpus = msm_platform_smp_prepare_cpus, Loading
arch/arm/mach-msm/platsmp.h +2 −1 Original line number Diff line number Diff line /* Copyright (c) 2012, The Linux Foundation. All rights reserved. /* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading @@ -19,5 +19,6 @@ int msm_cpu_kill(unsigned int cpu); extern struct smp_operations arm_smp_ops; extern struct smp_operations msm8960_smp_ops; extern struct smp_operations msm8974_smp_ops; extern struct smp_operations msm8962_smp_ops; extern struct smp_operations msm8625_smp_ops; extern struct smp_operations scorpion_smp_ops;