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Commit 7868ffcf authored by Bhalchandra Gajare's avatar Bhalchandra Gajare
Browse files

ASoC: msm8x10: Configure the codec external clock drive strength 



Whenever the codec external clock is enabled, configure the drive
strength on this clock before clock enable. This is to avoid possible
interference this clock can cause with other signals based on board
layout.

CRs-fixed: 551937
Change-Id: Ie45627424ce4f06dff96051ad18c55f4fb3279bc
Signed-off-by: default avatarBhalchandra Gajare <gajare@codeaurora.org>
parent fcdfb38c

sound/soc/msm/msm8x10.c

+5 −0
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ 
#include <qdsp6v2/msm-pcm-routing-v2.h>

#include <sound/q6afe-v2.h>

#include <linux/module.h>

#include <mach/gpiomux.h>

#include "../codecs/msm8x10-wcd.h"

#define DRV_NAME "msm8x10-asoc-wcd"

#define BTSCO_RATE_8KHZ 8000
@@ -186,6 +187,10 @@ static void msm8x10_enable_ext_spk_power_amp(u32 on) 


static int msm_config_mclk(u16 port_id, struct afe_digital_clk_cfg *cfg)

{

	/* set the drive strength on the clock */

	msm_tlmm_misc_reg_write(TLMM_CDC_HDRV_CTL, 0x00);

	msm_tlmm_misc_reg_write(TLMM_CDC_HDRV_PULL_CTL, 0x0006db6d);



	iowrite32(0x1, pcbcr);

	/* Set the update bit to make the settings go through */

	iowrite32(0x1, prcgr);