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Commit 77449519 authored by Sushmita Susheelendra's avatar Sushmita Susheelendra
Browse files

msm: kgsl: Support offset and size for cache operations 



Currently, IOCTL_KGSL_GPUMEM_SYNC_CACHE performs cache
operations on the entire memdesc. This change adds
support for performing the cache operation on a range
of memory defined by an offset and size

Change-Id: Icd8bf6f5a5c1a0335c6d278b950e19bdda0c95f6
Signed-off-by: default avatarSushmita Susheelendra <ssusheel@codeaurora.org>
parent 500bff85

drivers/gpu/msm/kgsl.c

+19 −6
Original line number Diff line number Diff line
@@ -2902,7 +2902,8 @@ error: 
	return result;

}



static int _kgsl_gpumem_sync_cache(struct kgsl_mem_entry *entry, int op)

static int _kgsl_gpumem_sync_cache(struct kgsl_mem_entry *entry,

				size_t offset, size_t length, unsigned int op)

{

	int ret = 0;

	int cacheop;
@@ -2925,11 +2926,17 @@ static int _kgsl_gpumem_sync_cache(struct kgsl_mem_entry *entry, int op) 
		goto done;

	}



	if (!(op & KGSL_GPUMEM_CACHE_RANGE)) {

		offset = 0;

		length = entry->memdesc.size;

	}



	mode = kgsl_memdesc_get_cachemode(&entry->memdesc);

	if (mode != KGSL_CACHEMODE_UNCACHED

		&& mode != KGSL_CACHEMODE_WRITECOMBINE) {

		trace_kgsl_mem_sync_cache(entry, op);

		kgsl_cache_range_op(&entry->memdesc, cacheop);

		trace_kgsl_mem_sync_cache(entry, offset, length, op);

		ret = kgsl_cache_range_op(&entry->memdesc, offset,

					length, cacheop);

	}



done:
@@ -2965,7 +2972,8 @@ long kgsl_ioctl_gpumem_sync_cache(struct kgsl_device_private *dev_priv, 
		return -EINVAL;

	}



	ret = _kgsl_gpumem_sync_cache(entry, param->op);

	ret = _kgsl_gpumem_sync_cache(entry, param->offset,

					param->length, param->op);

	kgsl_mem_entry_put(entry);

	return ret;

}
@@ -3050,9 +3058,13 @@ long kgsl_ioctl_gpumem_sync_cache_bulk(struct kgsl_device_private *dev_priv, 
		flush_cache_all();

	}



	param->op &= ~KGSL_GPUMEM_CACHE_RANGE;



	for (i = 0; i < actual_count; i++) {

		if (!full_flush)

			_kgsl_gpumem_sync_cache(entries[i], param->op);

			_kgsl_gpumem_sync_cache(entries[i], 0,

						entries[i]->memdesc.size,

						param->op);

		kgsl_mem_entry_put(entries[i]);

	}

end:
@@ -3079,7 +3091,8 @@ long kgsl_ioctl_sharedmem_flush_cache(struct kgsl_device_private *dev_priv, 
		return -EINVAL;

	}



	ret = _kgsl_gpumem_sync_cache(entry, KGSL_GPUMEM_CACHE_FLUSH);

	ret = _kgsl_gpumem_sync_cache(entry, 0, entry->memdesc.size,

					KGSL_GPUMEM_CACHE_FLUSH);

	kgsl_mem_entry_put(entry);

	return ret;

}

drivers/gpu/msm/kgsl_compat.c

+2 −0
Original line number Diff line number Diff line
@@ -156,6 +156,8 @@ kgsl_ioctl_gpumem_sync_cache_compat(struct kgsl_device_private *dev_priv, 
	param.gpuaddr = (unsigned long)param32->gpuaddr;

	param.id = param32->id;

	param.op = param32->op;

	param.offset = (size_t)param32->offset;

	param.length = (size_t)param32->length;



	return kgsl_ioctl_gpumem_sync_cache(dev_priv, cmd, &param);

}

drivers/gpu/msm/kgsl_compat.h

+2 −2
Original line number Diff line number Diff line
@@ -196,8 +196,8 @@ struct kgsl_gpumem_sync_cache_compat { 
	compat_ulong_t gpuaddr;

	unsigned int id;

	unsigned int op;

/* private: reserved for future use*/

	unsigned int __pad[2]; /* For future binary compatibility */

	compat_size_t length;

	compat_size_t offset;

};



#define IOCTL_KGSL_GPUMEM_SYNC_CACHE_COMPAT \

drivers/gpu/msm/kgsl_sharedmem.c

+14 −2
Original line number Diff line number Diff line
@@ -551,7 +551,8 @@ static struct kgsl_memdesc_ops kgsl_coherent_ops = { 
	.free = kgsl_coherent_free,

};



void kgsl_cache_range_op(struct kgsl_memdesc *memdesc, int op)

int kgsl_cache_range_op(struct kgsl_memdesc *memdesc, size_t offset,

			size_t size, unsigned int op)

{

	/*

	 * If the buffer is mapped in the kernel operate on that address
@@ -561,7 +562,16 @@ void kgsl_cache_range_op(struct kgsl_memdesc *memdesc, int op) 
	void *addr = (memdesc->hostptr) ?

		memdesc->hostptr : (void *) memdesc->useraddr;



	int size = memdesc->size;

	/* Check that offset+length does not exceed memdesc->size */

	if ((offset + size) > memdesc->size)

		return -ERANGE;



	addr = addr + offset;



	/*

	 * The dmac_xxx_range functions handle addresses and sizes that

	 * are not aligned to the cacheline size correctly.

	 */



	if (addr !=  NULL) {

		switch (op) {
@@ -577,6 +587,8 @@ void kgsl_cache_range_op(struct kgsl_memdesc *memdesc, int op) 
		}

	}

	outer_cache_range_op_sg(memdesc->sg, memdesc->sglen, op);



	return 0;

}

EXPORT_SYMBOL(kgsl_cache_range_op);

drivers/gpu/msm/kgsl_sharedmem.h

+3 −1
Original line number Diff line number Diff line
@@ -56,7 +56,9 @@ int kgsl_sharedmem_set(struct kgsl_device *device, 
			unsigned int offsetbytes, unsigned int value,

			unsigned int sizebytes);



void kgsl_cache_range_op(struct kgsl_memdesc *memdesc, int op);

int kgsl_cache_range_op(struct kgsl_memdesc *memdesc,

			size_t offset, size_t size,

			unsigned int op);



int kgsl_process_init_sysfs(struct kgsl_device *device,

		struct kgsl_process_private *private);