Loading arch/arm/boot/dts/qcom/msmzirc-coresight.dtsi +19 −0 Original line number Diff line number Diff line Loading @@ -371,4 +371,23 @@ coresight-name = "coresight-fuse-v2"; coresight-nr-inports = <0>; }; hwevent: hwevent@86c000 { compatible = "qcom,coresight-hwevent"; reg = <0x86c000 0x148>, <0x86cfb0 0x4>, <0x200c000 0xc>, <0x8B05010 0x4>, <0x7885010 0x4>, <0x801020 0x10>; reg-names = "wrapper-mux", "wrapper-lockaccess", "spmi-mux", "usbbam-mux", "blsp-mux", "apb-mux"; coresight-id = <23>; coresight-name = "coresight-hwevent"; coresight-nr-inports = <0>; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; }; }; Loading
arch/arm/boot/dts/qcom/msmzirc-coresight.dtsi +19 −0 Original line number Diff line number Diff line Loading @@ -371,4 +371,23 @@ coresight-name = "coresight-fuse-v2"; coresight-nr-inports = <0>; }; hwevent: hwevent@86c000 { compatible = "qcom,coresight-hwevent"; reg = <0x86c000 0x148>, <0x86cfb0 0x4>, <0x200c000 0xc>, <0x8B05010 0x4>, <0x7885010 0x4>, <0x801020 0x10>; reg-names = "wrapper-mux", "wrapper-lockaccess", "spmi-mux", "usbbam-mux", "blsp-mux", "apb-mux"; coresight-id = <23>; coresight-name = "coresight-hwevent"; coresight-nr-inports = <0>; clocks = <&clock_rpm clk_qdss_clk>, <&clock_rpm clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; }; };