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Commit 73b63efa authored by Jon Callan's avatar Jon Callan Committed by Catalin Marinas
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ARMv7: Add SMP initialisation to proc-v7.S 



This patch adds the SMP/nAMP mode setting to __v7_setup and also sets
TTBR to shared page table walks if SMP is enabled. The PTWs are also
marked inner cacheable for both SMP and UP modes (setting this is fine
even if the CPU doesn't support the feature).

Signed-off-by: default avatarJon Callan <Jon.Callan@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 6b07d7fe

arch/arm/mm/proc-v7.S

+15 −2
Original line number Diff line number Diff line
@@ -20,9 +20,17 @@ 


#define TTB_C		(1 << 0)

#define TTB_S		(1 << 1)

#define TTB_RGN_NC	(0 << 3)

#define TTB_RGN_OC_WBWA	(1 << 3)

#define TTB_RGN_OC_WT	(2 << 3)

#define TTB_RGN_OC_WB	(3 << 3)



#ifndef CONFIG_SMP

#define TTB_FLAGS	TTB_C|TTB_RGN_OC_WB		@ mark PTWs cacheable, outer WB

#else

#define TTB_FLAGS	TTB_C|TTB_S|TTB_RGN_OC_WBWA	@ mark PTWs cacheable and shared, outer WBWA

#endif



ENTRY(cpu_v7_proc_init)

	mov	pc, lr

ENDPROC(cpu_v7_proc_init)
@@ -85,7 +93,7 @@ ENTRY(cpu_v7_switch_mm) 
#ifdef CONFIG_MMU

	mov	r2, #0

	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id

	orr	r0, r0, #TTB_RGN_OC_WB		@ mark PTWs outer cacheable, WB

	orr	r0, r0, #TTB_FLAGS

	mcr	p15, 0, r2, c13, c0, 1		@ set reserved context ID

	isb

1:	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
@@ -162,6 +170,11 @@ cpu_v7_name: 
 *	- cache type register is implemented

 */

__v7_setup:

#ifdef CONFIG_SMP

	mrc	p15, 0, r0, c1, c0, 1		@ Enable SMP/nAMP mode

	orr	r0, r0, #(0x1 << 6)

	mcr	p15, 0, r0, c1, c0, 1

#endif

	adr	r12, __v7_setup_stack		@ the local stack

	stmia	r12, {r0-r5, r7, r9, r11, lr}

	bl	v7_flush_dcache_all
@@ -174,7 +187,7 @@ __v7_setup: 
#ifdef CONFIG_MMU

	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs

	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register

	orr	r4, r4, #TTB_RGN_OC_WB		@ mark PTWs outer cacheable, WB

	orr	r4, r4, #TTB_FLAGS

	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1

	mov	r10, #0x1f			@ domains 0, 1 = manager

	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register