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Commit 72554c9e authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: display: 8092 clock setting"

parents a24f6a5d 2c6840a8

arch/arm/mach-msm/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -86,7 +86,7 @@ obj-$(CONFIG_ARCH_MDM9630) += board-9630.o board-9630-gpiomux.o 
obj-$(CONFIG_ARCH_MSMSAMARIUM) += board-samarium.o board-samarium-gpiomux.o

obj-$(CONFIG_ARCH_MSMSAMARIUM) += clock-local2.o clock-pll.o clock-rpm.o clock-samarium.o clock-krait-8974.o clock-mdss-8974.o

obj-$(CONFIG_ARCH_MPQ8092) += board-8092.o board-8092-gpiomux.o

obj-$(CONFIG_ARCH_MPQ8092) += clock-local2.o clock-pll.o clock-rpm.o clock-voter.o clock-8092.o clock-vcap-8092.o

obj-$(CONFIG_ARCH_MPQ8092) += clock-local2.o clock-pll.o clock-rpm.o clock-voter.o clock-8092.o clock-vcap-8092.o clock-mdss-8974.o

obj-$(CONFIG_ARCH_MSM8226) += board-8226.o board-8226-gpiomux.o

obj-$(CONFIG_ARCH_MSM8226) += clock-local2.o clock-pll.o clock-8226.o clock-rpm.o clock-voter.o clock-mdss-8974.o

obj-$(CONFIG_ARCH_MSM8610) += board-8610.o board-8610-gpiomux.o

arch/arm/mach-msm/clock-8092.c

+67 −1
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 
#include "clock-rpm.h"

#include "clock-voter.h"

#include "clock.h"

#include "clock-mdss-8974.h"



enum {

	GCC_BASE,
@@ -467,7 +468,7 @@ static void __iomem *virt_bases[N_BASES]; 
#define mmpll3_mm_source_val		3

#define mmpll6_mm_source_val		2

#define gpll0_mm_source_val		5

#define hdmiphypll_mm_source_val	3

#define hdmipll_mm_source_val		3

#define lvdsphy0_pclk_mm_source_val	2

#define vbyonepll_pclk_mm_source_val	3

#define vbyonepll_sym_mm_source_val	4
@@ -3839,6 +3840,40 @@ static struct branch_clk mdss_hdmi_clk = { 
	},

};





static struct clk_freq_tbl ftbl_mdss_extpclk_clk[] = {

	F_MMSS(340000000, hdmipll, 1, 0, 0),

	F_END

};



static struct rcg_clk extpclk_clk_src = {

	.cmd_rcgr_reg = EXTPCLK_CMD_RCGR,

	.set_rate = set_rate_hid,

	.freq_tbl = ftbl_mdss_extpclk_clk,

	.current_freq = &rcg_dummy_freq,

	.base = &virt_bases[MMSS_BASE],

	.c = {

		.dbg_name = "extpclk_clk_src",

		.parent = &hdmipll_clk_src.c,

		.ops = &clk_ops_rcg_hdmi,

		VDD_DIG_FMAX_MAP2(LOW, 170000000, NOMINAL, 340000000),

		CLK_INIT(extpclk_clk_src.c),

	},

};



/* Allow set rate go through this branch clock */

static struct branch_clk mdss_extpclk_clk = {

	.cbcr_reg = MDSS_EXTPCLK_CBCR,

	.has_sibling = 0,

	.base = &virt_bases[MMSS_BASE],

	.c = {

		.parent = &extpclk_clk_src.c,

		.dbg_name = "mdss_extpclk_clk",

		.ops = &clk_ops_branch,

		CLK_INIT(mdss_extpclk_clk.c),

	},

};



static struct branch_clk mdss_mdp_clk = {

	.cbcr_reg = MDSS_MDP_CBCR,

	.has_sibling = 0,
@@ -5867,6 +5902,7 @@ struct measure_mux_entry measure_mux[] = { 
	{&venus0_ahb_clk.c,			MMSS_BASE,	0x000f},

	{&mdss_mdp_clk.c,			MMSS_BASE,	0x0012},

	{&mdss_mdp_lut_clk.c,			MMSS_BASE,	0x0013},

	{&mdss_extpclk_clk.c,			MMSS_BASE,	0x0014},

	{&mdss_hdmi_clk.c,			MMSS_BASE,	0x0019},

	{&mdss_ahb_clk.c,			MMSS_BASE,	0x001a},

	{&mdss_hdmi_ahb_clk.c,			MMSS_BASE,	0x001b},
@@ -6884,6 +6920,29 @@ static struct clk_lookup mpq_clocks_8092[] = { 
	CLK_LOOKUP("",	vpu_vdp_clk.c,	""),

	CLK_LOOKUP("",	vpu_vdp_xin_clk.c,	""),



	CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd900000.qcom,mdss_mdp"),

	CLK_LOOKUP("bus_clk", mdss_axi_clk.c, "fd900000.qcom,mdss_mdp"),

	CLK_LOOKUP("core_clk_src", mdp_clk_src.c, "fd900000.qcom,mdss_mdp"),

	CLK_LOOKUP("core_clk", mdss_mdp_clk.c, "fd900000.qcom,mdss_mdp"),

	CLK_LOOKUP("lut_clk", mdss_mdp_lut_clk.c, "fd900000.qcom,mdss_mdp"),

	CLK_LOOKUP("",	mdss_axi_clk.c, ""),

	CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd924100.qcom,hdmi_tx"),

	CLK_LOOKUP("alt_iface_clk", mdss_hdmi_ahb_clk.c,

		"fd924100.qcom,hdmi_tx"),

	CLK_LOOKUP("core_clk", mdss_hdmi_clk.c, "fd924100.qcom,hdmi_tx"),

	CLK_LOOKUP("mdp_core_clk", mdss_mdp_clk.c, "fd924100.qcom,hdmi_tx"),

	CLK_LOOKUP("extp_clk", mdss_extpclk_clk.c, "fd924100.qcom,hdmi_tx"),



	CLK_LOOKUP("",	mdss_mdp_clk.c, ""),

	CLK_LOOKUP("",	mdss_mdp_lut_clk.c, ""),



	CLK_LOOKUP("",	hdmipll_clk_src.c,	""),

	CLK_LOOKUP("",	hdmipll_mux_clk.c,	""),

	CLK_LOOKUP("",	hdmipll_div1_clk.c, ""),

	CLK_LOOKUP("",	hdmipll_div2_clk.c, ""),

	CLK_LOOKUP("",	hdmipll_div4_clk.c, ""),

	CLK_LOOKUP("",	hdmipll_div6_clk.c, ""),



	/* RCGs */

	CLK_LOOKUP("",	usb30_master_clk_src.c,	""),

	CLK_LOOKUP("",	tsif_ref_clk_src.c,	""),
@@ -7363,6 +7422,13 @@ static void __init mpq8092_clock_pre_init(void) 
	enable_rpm_scaling();



	reg_init();



	/*

	 * MDSS needs the ahb clock and needs to init before we register the

	 * lookup table.

	 */

	mdss_clk_update_hdmi_addr(0xFD924500, 0xFD924700);

	mdss_clk_ctrl_pre_init(&mdss_ahb_clk.c);

}



static void __init mpq8092_rumi_clock_pre_init(void)

arch/arm/mach-msm/clock-mdss-8974.c

+12 −3
Original line number Diff line number Diff line 
/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.

/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -163,6 +163,9 @@ static void __iomem *hdmi_phy_base; 
static void __iomem *hdmi_phy_pll_base;

static unsigned hdmi_pll_on;



static u32 hdmi_phy_addr = HDMI_PHY_PHYS;

static u32 hdmi_phy_pll_addr = HDMI_PHY_PLL_PHYS;



static int mdss_gdsc_enabled(void)

{

	if (!gdsc_base)
@@ -2844,6 +2847,12 @@ struct div_clk hdmipll_clk_src = { 
	},

};



void mdss_clk_update_hdmi_addr(u32 phy_addr, u32 phy_pll_addr)

{

	hdmi_phy_addr = phy_addr;

	hdmi_phy_pll_addr = phy_pll_addr;

}



void mdss_clk_ctrl_pre_init(struct clk *ahb_clk)

{

	BUG_ON(ahb_clk == NULL);
@@ -2858,11 +2867,11 @@ void mdss_clk_ctrl_pre_init(struct clk *ahb_clk) 


	mdss_ahb_clk = ahb_clk;



	hdmi_phy_base = ioremap(HDMI_PHY_PHYS, HDMI_PHY_SIZE);

	hdmi_phy_base = ioremap(hdmi_phy_addr, HDMI_PHY_SIZE);

	if (!hdmi_phy_base)

		pr_err("%s: unable to ioremap hdmi phy base", __func__);



	hdmi_phy_pll_base = ioremap(HDMI_PHY_PLL_PHYS, HDMI_PHY_PLL_SIZE);

	hdmi_phy_pll_base = ioremap(hdmi_phy_pll_addr, HDMI_PHY_PLL_SIZE);

	if (!hdmi_phy_pll_base)

		pr_err("%s: unable to ioremap hdmi phy pll base", __func__);

arch/arm/mach-msm/clock-mdss-8974.h

+2 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.

/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -20,6 +20,7 @@ 
extern struct clk_ops clk_ops_dsi_byte_pll;

extern struct clk_ops clk_ops_dsi_pixel_pll;



void mdss_clk_update_hdmi_addr(u32 phy_addr, u32 phy_pll_addr);

void mdss_clk_ctrl_pre_init(struct clk *ahb_clk);

void mdss_clk_ctrl_post_init(void);