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Commit 72300a81 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: use same label for rpm and gcc"

parents 0580b551 8e14ab31

arch/arm/boot/dts/qcom/msmtellurium-coresight.dtsi

+52 −52
Original line number Diff line number Diff line
@@ -27,8 +27,8 @@ 
		coresight-nr-inports = <1>;

		coresight-ctis = <&cti0 &cti8>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -44,8 +44,8 @@ 
		coresight-child-list = <&tmc_etr>;

		coresight-child-ports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -63,8 +63,8 @@ 
		coresight-default-sink;

		coresight-ctis = <&cti0 &cti8>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -80,8 +80,8 @@ 
		coresight-child-list = <&tmc_etf>;

		coresight-child-ports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -97,8 +97,8 @@ 
		coresight-child-list = <&funnel_merg>;

		coresight-child-ports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -114,8 +114,8 @@ 
		coresight-child-list = <&funnel_merg>;

		coresight-child-ports = <1>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -131,8 +131,8 @@ 
		coresight-child-list = <&funnel_in1>;

		coresight-child-ports = <6>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -149,8 +149,8 @@ 
		coresight-child-ports = <4>;

		coresight-etm-cpu = <&CPU0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -167,8 +167,8 @@ 
		coresight-child-ports = <5>;

		coresight-etm-cpu = <&CPU1>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -185,8 +185,8 @@ 
		coresight-child-ports = <6>;

		coresight-etm-cpu = <&CPU2>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -203,8 +203,8 @@ 
		coresight-child-ports = <7>;

		coresight-etm-cpu = <&CPU3>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -221,8 +221,8 @@ 
		coresight-child-ports = <0>;

		coresight-etm-cpu = <&CPU4>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -239,8 +239,8 @@ 
		coresight-child-ports = <1>;

		coresight-etm-cpu = <&CPU5>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -257,8 +257,8 @@ 
		coresight-child-ports = <2>;

		coresight-etm-cpu = <&CPU6>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -275,8 +275,8 @@ 
		coresight-child-ports = <3>;

		coresight-etm-cpu = <&CPU7>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -293,8 +293,8 @@ 
		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <7>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -308,8 +308,8 @@ 
		coresight-nr-inports = <0>;

		qcom,blk-size = <1>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -322,8 +322,8 @@ 
		coresight-name = "coresight-cti0";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -336,8 +336,8 @@ 
		coresight-name = "coresight-cti1";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -350,8 +350,8 @@ 
		coresight-name = "coresight-cti2";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -364,8 +364,8 @@ 
		coresight-name = "coresight-cti3";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -378,8 +378,8 @@ 
		coresight-name = "coresight-cti4";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -392,8 +392,8 @@ 
		coresight-name = "coresight-cti5";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -406,8 +406,8 @@ 
		coresight-name = "coresight-cti6";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -420,8 +420,8 @@ 
		coresight-name = "coresight-cti7";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};
@@ -434,8 +434,8 @@ 
		coresight-name = "coresight-cti8";

		coresight-nr-inports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};

arch/arm/boot/dts/qcom/msmtellurium.dtsi

+1 −6
Original line number Diff line number Diff line
@@ -124,11 +124,6 @@ 
		#clock-cells = <1>;

	};



	clock_rpm: qcom,rpmcc@1800000 {

		compatible = "qcom,dummycc";

		#clock-cells = <1>;

	};



	clock_debug: qcom,cc-debug@1874000 {

		compatible = "qcom,dummycc";

		#clock-cells = <1>;
@@ -416,7 +411,7 @@ 
		clocks = <&clock_gcc clk_gcc_usb_hs_ahb_clk>,

			 <&clock_gcc clk_gcc_usb_hs_system_clk>,

			 <&clock_gcc clk_gcc_usb2a_phy_sleep_clk>,

			 <&clock_rpm clk_xo_otg_clk>;

			 <&clock_gcc clk_xo_otg_clk>;

		clock-names = "iface_clk", "core_clk", "sleep_clk",

				"xo";

	};