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Commit 70d43ac5 authored by Taniya Das's avatar Taniya Das Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Support new speed bin and frequencies for 8916 



New cpu frequencies 1209.6MHz and 1152MHz will be supported under the
speed bin category. Speed bin (00) supports max of 1209.6MHz and (01)
supports max of 1152MHz.
Add corresponding cpr related changes for the new frequencies.

Change-Id: I74e7152eaa6546342b44a74decf4f50dc4b4a6b8
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent ccc80175

arch/arm/boot/dts/qcom/msm8916-regulator.dtsi

+7 −5
Original line number Diff line number Diff line
@@ -48,7 +48,7 @@ 
		regulator-name = "apc_corner";

		qcom,cpr-fuse-corners = <3>;

		regulator-min-microvolt = <1>;

		regulator-max-microvolt = <7>;

		regulator-max-microvolt = <8>;



		qcom,cpr-voltage-ceiling = <1050000 1150000 1350000>;

		qcom,cpr-voltage-floor = <1050000 1050000 1162500>;
@@ -85,7 +85,7 @@ 
					<27 0 6 0>;

		qcom,cpr-init-voltage-ref = <1050000 1150000 1350000>;

		qcom,cpr-init-voltage-step = <10000>;

		qcom,cpr-corner-map = <1 1 2 2 3 3 3>;

		qcom,cpr-corner-map = <1 1 2 2 3 3 3 3>;

		qcom,cpr-corner-frequency-map =

					<1 200000000>,

					<2 400000000>,
@@ -93,10 +93,12 @@ 
					<4 800000000>,

					<5 998400000>,

					<6 1094400000>,

					<7 1190400000>;

		qcom,speed-bin-fuse-sel = <1 34 3 0>;

					<7 1152000000>,

					<8 1209600000>;

		qcom,speed-bin-fuse-sel = <0 55 2 0>;

		qcom,cpr-speed-bin-max-corners =

					<0 0 2 4 7>;

					<0 0 2 4 8>,

					<1 0 2 4 7>;

		qcom,cpr-quot-adjust-scaling-factor-max = <650>;

		qcom,cpr-enable;

	};

arch/arm/boot/dts/qcom/msm8916.dtsi

+18 −5
Original line number Diff line number Diff line
@@ -293,8 +293,9 @@ 


	qcom,clock-a7@0b011050 {

		compatible = "qcom,clock-a53-8916";

		reg = <0x0b011050 0x8>;

		reg-names = "rcg-base";

		reg = <0x0b011050 0x8>,

		      <0x0005c004 0x8>;

		reg-names = "rcg-base", "efuse1";

		qcom,safe-freq = < 400000000 >;

		cpu-vdd-supply = <&apc_vreg_corner>;

		clocks = <&clock_gcc clk_gpll0_ao_clk_src>,
@@ -308,7 +309,18 @@ 
			<  800000000 4>,

			<  998400000 5>,

			< 1094400000 6>,

			< 1190400000 7>;

			< 1152000000 7>,

			< 1209600000 8>;



		qcom,speed1-bin-v0 =

			<          0 0>,

			<  200000000 1>,

			<  400000000 2>,

			<  533333000 3>,

			<  800000000 4>,

			<  998400000 5>,

			< 1094400000 6>,

			< 1152000000 7>;

	};



	cpubw: qcom,cpubw {
@@ -338,7 +350,7 @@ 
				 <  400000  762>,

				 <  998400  1525>,

				 < 1094400  3051>,

				 < 1190400  4066>;

				 < 1152000  4066>;

		};

	};
@@ -352,7 +364,8 @@ 
			 <  800000 >,

			 <  998400 >,

			 < 1094400 >,

			 < 1190400 >;

			 < 1152000 >,

			 < 1209600 >;

	};



	qcom,sps {