Loading arch/arm/boot/dts/qcom/msmferrum-pinctrl.dtsi +19 −0 Original line number Diff line number Diff line Loading @@ -199,5 +199,24 @@ }; }; pmx_i2c_5 { /* CLK, DATA */ qcom,pins = <&gp 19>, <&gp 18>; qcom,num-grp-pins = <2>; qcom,pin-func = <2>; label = "pmx_i2c_5"; i2c_5_active: i2c_5_active { drive-strength = <2>; /* 2 MA */ bias-disable = <0>; /* No PULL */ }; i2c_5_sleep: i2c_5_sleep { drive-strength = <2>; /* 2 MA */ bias-disable = <0>; /* No PULL */ }; }; }; }; arch/arm/boot/dts/qcom/msmferrum.dtsi +26 −0 Original line number Diff line number Diff line Loading @@ -35,6 +35,7 @@ sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ sdhc2 = &sdhc_2; /* SDC2 SD card slot */ spi0 = &spi_0; /* SPI0 controller device */ i2c5 = &i2c_5; /* I2c5 cntroller device */ }; cpus { Loading Loading @@ -521,6 +522,31 @@ qcom,master-id = <86>; }; i2c_5: i2c@78b9000 { /* BLSP1 QUP5 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "qup_phys_addr", "bam_phys_addr"; reg = <0x78b9000 0x1000>, <0x7884000 0x23000>; interrupt-names = "qup_irq", "bam_irq"; interrupts = <0 99 0>, <0 238 0>; clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, <&clock_gcc clk_gcc_blsp1_qup5_i2c_apps_clk>; clock-names = "iface_clk", "core_clk"; qcom,clk-freq-out = <100000>; qcom,clk-freq-in = <19200000>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_5_active>; pinctrl-1 = <&i2c_5_sleep>; qcom,noise-rjct-scl = <0>; qcom,noise-rjct-sda = <0>; qcom,bam-pipe-idx-cons = <12>; qcom,bam-pipe-idx-prod = <13>; qcom,master-id = <86>; }; }; Loading Loading
arch/arm/boot/dts/qcom/msmferrum-pinctrl.dtsi +19 −0 Original line number Diff line number Diff line Loading @@ -199,5 +199,24 @@ }; }; pmx_i2c_5 { /* CLK, DATA */ qcom,pins = <&gp 19>, <&gp 18>; qcom,num-grp-pins = <2>; qcom,pin-func = <2>; label = "pmx_i2c_5"; i2c_5_active: i2c_5_active { drive-strength = <2>; /* 2 MA */ bias-disable = <0>; /* No PULL */ }; i2c_5_sleep: i2c_5_sleep { drive-strength = <2>; /* 2 MA */ bias-disable = <0>; /* No PULL */ }; }; }; };
arch/arm/boot/dts/qcom/msmferrum.dtsi +26 −0 Original line number Diff line number Diff line Loading @@ -35,6 +35,7 @@ sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ sdhc2 = &sdhc_2; /* SDC2 SD card slot */ spi0 = &spi_0; /* SPI0 controller device */ i2c5 = &i2c_5; /* I2c5 cntroller device */ }; cpus { Loading Loading @@ -521,6 +522,31 @@ qcom,master-id = <86>; }; i2c_5: i2c@78b9000 { /* BLSP1 QUP5 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "qup_phys_addr", "bam_phys_addr"; reg = <0x78b9000 0x1000>, <0x7884000 0x23000>; interrupt-names = "qup_irq", "bam_irq"; interrupts = <0 99 0>, <0 238 0>; clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, <&clock_gcc clk_gcc_blsp1_qup5_i2c_apps_clk>; clock-names = "iface_clk", "core_clk"; qcom,clk-freq-out = <100000>; qcom,clk-freq-in = <19200000>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_5_active>; pinctrl-1 = <&i2c_5_sleep>; qcom,noise-rjct-scl = <0>; qcom,noise-rjct-sda = <0>; qcom,bam-pipe-idx-cons = <12>; qcom,bam-pipe-idx-prod = <13>; qcom,master-id = <86>; }; }; Loading