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Commit 6d843a6b authored by Huaibin Yang's avatar Huaibin Yang
Browse files

msm: mdss: calculate mdp clk requirement of each pipe with the fudge factor 



Currently the mdp clk margin is added for the final calculated max of
all individual pipe clk requirements to avoid underruns. When this
final rate is greater than the max rate that h/w can support, pipe
decimation mode may not be enabled to avoid underruns. So, move this
margin calculation into each pipe clk so that when any individual pipe
has higher clk rate than the max, pipe decimation can be enabled.

CRs-fixed: 538803
Change-Id: Ia4dc500cfc27e7e4d08f03066b511ed3e4ae4664
Signed-off-by: default avatarHuaibin Yang <huaibiny@codeaurora.org>
parent 02983880

drivers/video/msm/mdss/mdss_mdp_ctl.c

+24 −3
Original line number Diff line number Diff line
@@ -69,6 +69,25 @@ static inline u32 mdss_mdp_get_pclk_rate(struct mdss_mdp_ctl *ctl) 
		pinfo->clk_rate;

}



static inline u32 mdss_mdp_clk_fudge_factor(struct mdss_mdp_mixer *mixer,

						u32 rate)

{

	struct mdss_panel_info *pinfo = &mixer->ctl->panel_data->panel_info;



	rate = CLK_FUDGE_FACTOR(rate);



	/*

	 * If the panel is video mode and its back porch period is

	 * small, the workaround of increasing mdp clk is needed to

	 * avoid underrun.

	 */

	if (mixer->ctl->is_video_mode && pinfo &&

		(pinfo->lcdc.v_back_porch < MDP_MIN_VBP))

		rate = CLK_FUDGE_FACTOR(rate);



	return rate;

}



static u32 __mdss_mdp_ctrl_perf_ovrd_helper(struct mdss_mdp_mixer *mixer,

		u32 *npipe)

{
@@ -168,7 +187,6 @@ static int mdss_mdp_ctl_perf_commit(struct mdss_data_type *mdata, u32 flags) 
		mdss_mdp_bus_scale_set_quota(bus_ab_quota, bus_ib_quota);

	}

	if (flags & MDSS_MDP_PERF_UPDATE_CLK) {

		clk_rate = CLK_FUDGE_FACTOR(clk_rate);

		pr_debug("update clk rate = %lu HZ\n", clk_rate);

		mdss_mdp_set_clk_rate(clk_rate);

	}
@@ -252,8 +270,12 @@ int mdss_mdp_perf_calc_pipe(struct mdss_mdp_pipe *pipe, 
	}



	perf->ab_quota = quota;

	rate = mdss_mdp_clk_fudge_factor(mixer, rate);

	perf->mdp_clk_rate = rate;



	pr_debug("src(w,h)(%d,%d) dst(w,h)(%d,%d) v_total=%d v_deci=%d fps=%d\n",

		pipe->src.w, pipe->src.h, pipe->dst.w, pipe->dst.h, v_total,

		pipe->vert_deci, fps);

	pr_debug("mixer=%d pnum=%d clk_rate=%u bus ab=%u ib=%u\n",

		 mixer->num, pipe->num, rate, perf->ab_quota, perf->ib_quota);
@@ -287,8 +309,7 @@ static void mdss_mdp_perf_mixer_update(struct mdss_mdp_mixer *mixer, 
			v_total = mixer->height;

		}

		*clk_rate = mixer->width * v_total * fps;

		if (pinfo && pinfo->lcdc.v_back_porch < MDP_MIN_VBP)

			*clk_rate = CLK_FUDGE_FACTOR(*clk_rate);

		*clk_rate = mdss_mdp_clk_fudge_factor(mixer, *clk_rate);



		if (!pinfo) {

			/* perf for bus writeback */