Loading Documentation/devicetree/bindings/usb/dwc3.txt +3 −0 Original line number Diff line number Diff line Loading @@ -25,6 +25,9 @@ Optional properties: controls the UTMI sleep mechanism vs. the PHY. Default value is 12. - snps,bus-suspend-enable: If present then controller supports low power mode during bus suspend. - snps,lpm-nyet-thresh: If present, will determine the value of DCTL[LPM_NYET_Thres]. If BESL value received from the host in the LPM token is less than this value we send LPM ACK to the host. Otherwise the device returns LPM NYET. This is usually a subnode to DWC3 glue to which it is connected. Loading drivers/usb/dwc3/core.c +6 −0 Original line number Diff line number Diff line Loading @@ -564,6 +564,7 @@ static int dwc3_probe(struct platform_device *pdev) void *mem; u32 hird_thresh; u32 lpm_nyet_thresh; u8 mode; bool host_only_mode; Loading Loading @@ -629,6 +630,11 @@ static int dwc3_probe(struct platform_device *pdev) else dwc->hird_thresh = DWC3_DCTL_HIRD_THRES_DEFAULT; ret = of_property_read_u32(node, "snps,lpm-nyet-thresh", &lpm_nyet_thresh); if (!ret) dwc->lpm_nyet_thresh = (u8)lpm_nyet_thresh; dwc->enable_bus_suspend = of_property_read_bool(node, "snps,bus-suspend-enable"); Loading drivers/usb/dwc3/core.h +5 −0 Original line number Diff line number Diff line Loading @@ -262,6 +262,9 @@ #define DWC3_DCTL_APPL1RES (1 << 23) #define DWC3_DCTL_LPM_NYET_THRES_MASK (0x0f << 20) #define DWC3_DCTL_LPM_NYET_THRES(n) ((n) << 20) /* These apply for core versions 1.87a and earlier */ #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) #define DWC3_DCTL_TRGTULST(n) ((n) << 17) Loading Loading @@ -784,6 +787,7 @@ struct dwc3_scratchpad_array { * during disconnect and set it after device is configured. * @usb3_u1u2_disable: if true, disable U1U2 low power modes in Superspeed mode. * @hird_thresh: value to configure in DCTL[HIRD_Thresh] * @lpm_nyet_thresh: value to configure in DCTL[LPM_NYET_Thresh] * @in_lpm: if 1, indicates that the controller is in low power mode (no clocks) * @irq: irq number * @bh: tasklet which handles the interrupt Loading Loading @@ -902,6 +906,7 @@ struct dwc3 { bool usb3_u1u2_disable; bool enable_bus_suspend; u8 hird_thresh; u8 lpm_nyet_thresh; atomic_t in_lpm; struct dwc3_gadget_events dbg_gadget_events; Loading drivers/usb/dwc3/gadget.c +10 −0 Original line number Diff line number Diff line Loading @@ -3033,6 +3033,16 @@ static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_thresh); /* * If USB2.0 LPM ECN Errata is enabled in DWC Core then set * LPM_NYET_THRESH. */ if (dwc->revision >= DWC3_REVISION_240A && dwc->lpm_nyet_thresh) { reg &= ~DWC3_DCTL_LPM_NYET_THRES_MASK; reg |= DWC3_DCTL_LPM_NYET_THRES(dwc->lpm_nyet_thresh); } dwc3_writel(dwc->regs, DWC3_DCTL, reg); } Loading Loading
Documentation/devicetree/bindings/usb/dwc3.txt +3 −0 Original line number Diff line number Diff line Loading @@ -25,6 +25,9 @@ Optional properties: controls the UTMI sleep mechanism vs. the PHY. Default value is 12. - snps,bus-suspend-enable: If present then controller supports low power mode during bus suspend. - snps,lpm-nyet-thresh: If present, will determine the value of DCTL[LPM_NYET_Thres]. If BESL value received from the host in the LPM token is less than this value we send LPM ACK to the host. Otherwise the device returns LPM NYET. This is usually a subnode to DWC3 glue to which it is connected. Loading
drivers/usb/dwc3/core.c +6 −0 Original line number Diff line number Diff line Loading @@ -564,6 +564,7 @@ static int dwc3_probe(struct platform_device *pdev) void *mem; u32 hird_thresh; u32 lpm_nyet_thresh; u8 mode; bool host_only_mode; Loading Loading @@ -629,6 +630,11 @@ static int dwc3_probe(struct platform_device *pdev) else dwc->hird_thresh = DWC3_DCTL_HIRD_THRES_DEFAULT; ret = of_property_read_u32(node, "snps,lpm-nyet-thresh", &lpm_nyet_thresh); if (!ret) dwc->lpm_nyet_thresh = (u8)lpm_nyet_thresh; dwc->enable_bus_suspend = of_property_read_bool(node, "snps,bus-suspend-enable"); Loading
drivers/usb/dwc3/core.h +5 −0 Original line number Diff line number Diff line Loading @@ -262,6 +262,9 @@ #define DWC3_DCTL_APPL1RES (1 << 23) #define DWC3_DCTL_LPM_NYET_THRES_MASK (0x0f << 20) #define DWC3_DCTL_LPM_NYET_THRES(n) ((n) << 20) /* These apply for core versions 1.87a and earlier */ #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) #define DWC3_DCTL_TRGTULST(n) ((n) << 17) Loading Loading @@ -784,6 +787,7 @@ struct dwc3_scratchpad_array { * during disconnect and set it after device is configured. * @usb3_u1u2_disable: if true, disable U1U2 low power modes in Superspeed mode. * @hird_thresh: value to configure in DCTL[HIRD_Thresh] * @lpm_nyet_thresh: value to configure in DCTL[LPM_NYET_Thresh] * @in_lpm: if 1, indicates that the controller is in low power mode (no clocks) * @irq: irq number * @bh: tasklet which handles the interrupt Loading Loading @@ -902,6 +906,7 @@ struct dwc3 { bool usb3_u1u2_disable; bool enable_bus_suspend; u8 hird_thresh; u8 lpm_nyet_thresh; atomic_t in_lpm; struct dwc3_gadget_events dbg_gadget_events; Loading
drivers/usb/dwc3/gadget.c +10 −0 Original line number Diff line number Diff line Loading @@ -3033,6 +3033,16 @@ static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_thresh); /* * If USB2.0 LPM ECN Errata is enabled in DWC Core then set * LPM_NYET_THRESH. */ if (dwc->revision >= DWC3_REVISION_240A && dwc->lpm_nyet_thresh) { reg &= ~DWC3_DCTL_LPM_NYET_THRES_MASK; reg |= DWC3_DCTL_LPM_NYET_THRES(dwc->lpm_nyet_thresh); } dwc3_writel(dwc->regs, DWC3_DCTL, reg); } Loading