Loading drivers/mmc/host/sdhci-msm.c +3 −1 Original line number Diff line number Diff line Loading @@ -2897,11 +2897,13 @@ static void sdhci_set_default_hw_caps(struct sdhci_msm_host *msm_host, /* * Starting with SDCC 5 controller (core major version = 1) * controller won't advertise 3.0v features except for * controller won't advertise 3.0v and 8-bit features except for * some targets. */ if (major >= 1 && minor != 0x11 && minor != 0x12) { caps = CORE_3_0V_SUPPORT; if (msm_host->pdata->mmc_bus_width == MMC_CAP_8_BIT_DATA) caps |= CORE_8_BIT_SUPPORT; writel_relaxed( (readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES) | caps), host->ioaddr + CORE_VENDOR_SPEC_CAPABILITIES0); Loading Loading
drivers/mmc/host/sdhci-msm.c +3 −1 Original line number Diff line number Diff line Loading @@ -2897,11 +2897,13 @@ static void sdhci_set_default_hw_caps(struct sdhci_msm_host *msm_host, /* * Starting with SDCC 5 controller (core major version = 1) * controller won't advertise 3.0v features except for * controller won't advertise 3.0v and 8-bit features except for * some targets. */ if (major >= 1 && minor != 0x11 && minor != 0x12) { caps = CORE_3_0V_SUPPORT; if (msm_host->pdata->mmc_bus_width == MMC_CAP_8_BIT_DATA) caps |= CORE_8_BIT_SUPPORT; writel_relaxed( (readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES) | caps), host->ioaddr + CORE_VENDOR_SPEC_CAPABILITIES0); Loading