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Commit 6bddb3c7 authored by Tianyi Gou's avatar Tianyi Gou
Browse files

msm: clock-8084: Update mmss axi clock max freq 



Latest frequency table shows mmss axi clock can only run
up to 400MHz. Therefore, update the sw to match with the
data.

Change-Id: I8ca0e0f6461aafae82baddfc68c1e4c9dd7192c1
Signed-off-by: default avatarTianyi Gou <tgou@codeaurora.org>
parent fe59e87b

arch/arm/mach-msm/clock-8084.c

+1 −2
Original line number Diff line number Diff line
@@ -3451,7 +3451,6 @@ static struct clk_freq_tbl ftbl_mmss_axi_clk[] = { 
	F_MM(150000000,  gpll0,     4,   0,   0),

	F_MM(333430000, mmpll1,   3.5,   0,   0),

	F_MM(400000000, mmpll0,     2,   0,   0),

	F_MM(466800000, mmpll1,   2.5,   0,   0),

	F_END

};
@@ -3465,7 +3464,7 @@ static struct rcg_clk axi_clk_src = { 
		.dbg_name = "axi_clk_src",

		.ops = &clk_ops_rcg,

		VDD_DIG_FMAX_MAP3(LOW, 150000000, NOMINAL, 333430000,

				  HIGH, 466800000),

				  HIGH, 400000000),

		CLK_INIT(axi_clk_src.c),

	},

};