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Commit 6a7d6fe7 authored by Murali Nalajala's avatar Murali Nalajala
Browse files

msm: msm-pm: use proper co-processor instructions 



Existing assembly instructions are not valid
for AArch64 mode for ARMv8 targets. Use proper
co-processor instructions for AArch64 mode for
ARMv8 targets to read the cache properties.

Change-Id: If4e97d5016e0bd52d7e57b5639e200b3601e0412
Signed-off-by: default avatarMurali Nalajala <mnalajal@codeaurora.org>
parent 9b02e768

arch/arm/mach-msm/msm-pm.c

+14 −1
Original line number Original line Diff line number Diff line
@@ -157,14 +157,27 @@ static inline void msm_arch_idle(void) 




static bool msm_pm_is_L1_writeback(void)

static bool msm_pm_is_L1_writeback(void)

{

{

	u32 sel = 0, cache_id;

	u32 cache_id;





#if defined(CONFIG_CPU_V7)

	u32 sel = 0;

	asm volatile ("mcr p15, 2, %[ccselr], c0, c0, 0\n\t"

	asm volatile ("mcr p15, 2, %[ccselr], c0, c0, 0\n\t"

		      "isb\n\t"

		      "isb\n\t"

		      "mrc p15, 1, %[ccsidr], c0, c0, 0\n\t"

		      "mrc p15, 1, %[ccsidr], c0, c0, 0\n\t"

		      :[ccsidr]"=r" (cache_id)

		      :[ccsidr]"=r" (cache_id)

		      :[ccselr]"r" (sel)

		      :[ccselr]"r" (sel)

		     );

		     );

#elif defined(CONFIG_ARM64)

	u32 sel = 0;

	asm volatile("msr csselr_el1, %[ccselr]\n\t"

		     "isb\n\t"

		     "mrs %[ccsidr],ccsidr_el1\n\t"

		     :[ccsidr]"=r" (cache_id)

		     :[ccselr]"r" (sel)

		    );

#else

#error No valid CPU arch selected

#endif

	return cache_id & BIT(31);

	return cache_id & BIT(31);

}

}