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Commit 693ffaa9 authored by Tony Truong's avatar Tony Truong Committed by Gerrit - the friendly Code Review server
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msm: pcie: add vbg optimization support 



Add support to configure the settings to enable
vbg optimization.

Change-Id: I831e9405123ac0ae20817c60f58e50203738e977
Signed-off-by: default avatarTony Truong <truong@codeaurora.org>
parent 8bcee50a

Documentation/devicetree/bindings/pci/msm_pcie.txt

+2 −0
Original line number Diff line number Diff line
@@ -66,6 +66,7 @@ Optional Properties: 
  - qcom,msi-gicm-addr: MSI address for GICv2m.

  - qcom,msi-gicm-base: MSI IRQ base for GICv2m.

  - qcom,ext-ref-clk: The reference clock is external.

  - qcom,vbg-opt: The vbg optimization is supported.

  - qcom,ep-latency: The time (unit: ms) to wait for the PCIe endpoint to become

    stable after power on, before de-assert the PERST to the endpoint.

  - qcom,tlp-rd-size: The max TLP read size (Calculation: 128 times 2 to the
@@ -156,6 +157,7 @@ Example: 
		qcom,msi-gicm-addr = <0xf9040040>;

		qcom,msi-gicm-base = <0x160>;

		qcom,ext-ref-clk;

		qcom,vbg-opt;

		qcom,tlp-rd-size = <0x5>;

		qcom,ep-latency = <100>;

drivers/pci/host/pci-msm.c

+20 −2
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@ 
#define QSERDES_COM_PLLLOCK_CMP1	0x090

#define QSERDES_COM_PLLLOCK_CMP2	0x094

#define QSERDES_COM_PLLLOCK_CMP_EN	0x09C

#define QSERDES_COM_BGTC		0x0A0

#define QSERDES_COM_DEC_START1	0x0AC

#define QSERDES_COM_RES_CODE_START_SEG1	0x0E0

#define QSERDES_COM_RES_CODE_CAL_CSR	0x0E8
@@ -498,6 +499,7 @@ struct msm_pcie_dev_t { 
	bool				 aux_clk_sync;

	uint32_t			   n_fts;

	bool				 ext_ref_clk;

	bool				vbg_opt;

	uint32_t			   ep_latency;

	uint32_t			current_bdf;

	uint32_t			tlp_rd_size;
@@ -984,8 +986,16 @@ static void pcie_phy_init(struct msm_pcie_dev_t *dev) 
	msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_IP_SETP, 0x12);

	msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_CP_SETP, 0x0F);

	msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_IP_SETI, 0x01);



	if (dev->vbg_opt) {

		msm_pcie_write_reg(dev->phy, QSERDES_COM_IE_TRIM, 0x03);

		msm_pcie_write_reg(dev->phy, QSERDES_COM_IP_TRIM, 0x00);

		msm_pcie_write_reg(dev->phy, QSERDES_COM_BGTC, 0xFF);

	} else {

		msm_pcie_write_reg(dev->phy, QSERDES_COM_IE_TRIM, 0x0F);

		msm_pcie_write_reg(dev->phy, QSERDES_COM_IP_TRIM, 0x0F);

	}



	msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_CNTRL, 0x46);



	/* CDR Settings */
@@ -1243,6 +1253,8 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev) 
		dev->aux_clk_sync);

	pr_alert("ext_ref_clk is %d\n",

		dev->ext_ref_clk);

	pr_alert("vbg_opt is %s supported\n",

		dev->vbg_opt ? "" : "not");

	pr_alert("ep_wakeirq is %d\n",

		dev->ep_wakeirq);

	pr_alert("drv_ready is %d\n",
@@ -4587,6 +4599,12 @@ static int msm_pcie_probe(struct platform_device *pdev) 
	PCIE_DBG(&msm_pcie_dev[rc_idx], "ref clk is %s.\n",

		msm_pcie_dev[rc_idx].ext_ref_clk ? "external" : "internal");



	msm_pcie_dev[rc_idx].vbg_opt =

		of_property_read_bool((&pdev->dev)->of_node,

				"qcom,vbg-opt");

	PCIE_DBG(&msm_pcie_dev[rc_idx], "vbg opt is %s supported.\n",

		msm_pcie_dev[rc_idx].vbg_opt ? "" : "not");



	msm_pcie_dev[rc_idx].ep_latency = 0;

	ret = of_property_read_u32((&pdev->dev)->of_node,

				"qcom,ep-latency",