Loading arch/arm/boot/dts/qti/msmkrypton-regulator.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -100,6 +100,7 @@ regulator-min-microvolt = <1>; regulator-max-microvolt = <7>; qcom,use-voltage-corner; qcom,consumer-supplies = "vdd_dig_ao", ""; }; pmd9635_l3_floor_corner: regulator-l3-floor-corner { compatible = "qcom,rpm-regulator-smd"; Loading arch/arm/boot/dts/qti/msmkrypton.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -627,7 +627,7 @@ < 748800000 5>, < 998400000 7>; cpu-vdd-supply = <&pmd9635_l3_corner>; cpu-vdd-supply = <&pmd9635_l3_corner_ao>; }; qcom,msm-cpufreq@0 { Loading arch/arm/mach-msm/clock-krypton.c +14 −1 Original line number Diff line number Diff line Loading @@ -100,6 +100,13 @@ static void __iomem *virt_bases[N_BASES]; [VDD_DIG_##l3] = (f3), \ }, \ .num_fmax = VDD_DIG_NUM #define VDD_DIG_FMAX_MAP2_AO(l1, f1, l2, f2) \ .vdd_class = &vdd_dig_ao, \ .fmax = (unsigned long[VDD_DIG_NUM]) { \ [VDD_DIG_##l1] = (f1), \ [VDD_DIG_##l2] = (f2), \ }, \ .num_fmax = VDD_DIG_NUM enum vdd_dig_levels { VDD_DIG_NONE, Loading Loading @@ -1666,6 +1673,8 @@ static struct alpha_pll_vco_tbl alpha_pll_vco_20nm_p[] = { VCO(0, 1500000000, 2000000000), }; static DEFINE_VDD_REGULATORS(vdd_dig_ao, VDD_DIG_NUM, 1, vdd_corner, NULL); static struct alpha_pll_clk a7sspll = { .masks = &alpha_pll_masks_20nm_p, .base = &virt_bases[APCS_ACC_BASE], Loading @@ -1675,7 +1684,7 @@ static struct alpha_pll_clk a7sspll = { .parent = &xo_a_clk.c, .dbg_name = "a7sspll", .ops = &clk_ops_alpha_pll, VDD_DIG_FMAX_MAP2(LOW, 1000000000, NOMINAL, 2000000000), VDD_DIG_FMAX_MAP2_AO(LOW, 1000000000, NOMINAL, 2000000000), CLK_INIT(a7sspll.c), }, }; Loading Loading @@ -2252,6 +2261,10 @@ static void __init msmkrypton_clock_pre_init(void) if (IS_ERR(vdd_dig.regulator[0])) panic("clock-krypton: Unable to get the vdd_dig regulator!"); vdd_dig_ao.regulator[0] = regulator_get(NULL, "vdd_dig_ao"); if (IS_ERR(vdd_dig_ao.regulator[0])) panic("clock-krypton: Unable to get the vdd_dig_ao regulator!"); enable_rpm_scaling(); reg_init(); Loading Loading
arch/arm/boot/dts/qti/msmkrypton-regulator.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -100,6 +100,7 @@ regulator-min-microvolt = <1>; regulator-max-microvolt = <7>; qcom,use-voltage-corner; qcom,consumer-supplies = "vdd_dig_ao", ""; }; pmd9635_l3_floor_corner: regulator-l3-floor-corner { compatible = "qcom,rpm-regulator-smd"; Loading
arch/arm/boot/dts/qti/msmkrypton.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -627,7 +627,7 @@ < 748800000 5>, < 998400000 7>; cpu-vdd-supply = <&pmd9635_l3_corner>; cpu-vdd-supply = <&pmd9635_l3_corner_ao>; }; qcom,msm-cpufreq@0 { Loading
arch/arm/mach-msm/clock-krypton.c +14 −1 Original line number Diff line number Diff line Loading @@ -100,6 +100,13 @@ static void __iomem *virt_bases[N_BASES]; [VDD_DIG_##l3] = (f3), \ }, \ .num_fmax = VDD_DIG_NUM #define VDD_DIG_FMAX_MAP2_AO(l1, f1, l2, f2) \ .vdd_class = &vdd_dig_ao, \ .fmax = (unsigned long[VDD_DIG_NUM]) { \ [VDD_DIG_##l1] = (f1), \ [VDD_DIG_##l2] = (f2), \ }, \ .num_fmax = VDD_DIG_NUM enum vdd_dig_levels { VDD_DIG_NONE, Loading Loading @@ -1666,6 +1673,8 @@ static struct alpha_pll_vco_tbl alpha_pll_vco_20nm_p[] = { VCO(0, 1500000000, 2000000000), }; static DEFINE_VDD_REGULATORS(vdd_dig_ao, VDD_DIG_NUM, 1, vdd_corner, NULL); static struct alpha_pll_clk a7sspll = { .masks = &alpha_pll_masks_20nm_p, .base = &virt_bases[APCS_ACC_BASE], Loading @@ -1675,7 +1684,7 @@ static struct alpha_pll_clk a7sspll = { .parent = &xo_a_clk.c, .dbg_name = "a7sspll", .ops = &clk_ops_alpha_pll, VDD_DIG_FMAX_MAP2(LOW, 1000000000, NOMINAL, 2000000000), VDD_DIG_FMAX_MAP2_AO(LOW, 1000000000, NOMINAL, 2000000000), CLK_INIT(a7sspll.c), }, }; Loading Loading @@ -2252,6 +2261,10 @@ static void __init msmkrypton_clock_pre_init(void) if (IS_ERR(vdd_dig.regulator[0])) panic("clock-krypton: Unable to get the vdd_dig regulator!"); vdd_dig_ao.regulator[0] = regulator_get(NULL, "vdd_dig_ao"); if (IS_ERR(vdd_dig_ao.regulator[0])) panic("clock-krypton: Unable to get the vdd_dig_ao regulator!"); enable_rpm_scaling(); reg_init(); Loading