Loading drivers/clk/qcom/clock-gcc-8994.c +7 −0 Original line number Diff line number Diff line Loading @@ -2473,6 +2473,10 @@ static struct branch_clk gcc_usb_phy_cfg_ahb2phy_clk = { }, }; DEFINE_CLK_DUMMY(cci_clk, 150000000); DEFINE_CLK_DUMMY(a53_clk, 250000000); DEFINE_CLK_DUMMY(a57_clk, 250000000); static struct mux_clk gcc_debug_mux; static struct clk_ops clk_ops_debug_mux; static struct clk_mux_ops gcc_debug_mux_ops; Loading Loading @@ -2773,6 +2777,9 @@ static struct clk_lookup msm_clocks_gcc_8994[] = { CLK_LIST(gcc_usb_hs_ahb_clk), CLK_LIST(gcc_usb_hs_system_clk), CLK_LIST(gcc_usb_phy_cfg_ahb2phy_clk), CLK_LIST(cci_clk), CLK_LIST(a53_clk), CLK_LIST(a57_clk), }; static int msm_gcc_8994_probe(struct platform_device *pdev) Loading include/dt-bindings/clock/msm-clocks-8994.h +5 −0 Original line number Diff line number Diff line Loading @@ -384,6 +384,11 @@ #define clk_mdss_pclk0_clk 0x3487234a #define clk_mdss_pclk1_clk 0xd5804246 /* clock_cpu controlled clocks */ #define clk_cci_clk 0x96854074 #define clk_a53_clk 0x5c9f8836 #define clk_a57_clk 0x6c7dc3ea /* clock_debug controlled clocks */ #define clk_gcc_debug_mux 0x8121ac15 Loading Loading
drivers/clk/qcom/clock-gcc-8994.c +7 −0 Original line number Diff line number Diff line Loading @@ -2473,6 +2473,10 @@ static struct branch_clk gcc_usb_phy_cfg_ahb2phy_clk = { }, }; DEFINE_CLK_DUMMY(cci_clk, 150000000); DEFINE_CLK_DUMMY(a53_clk, 250000000); DEFINE_CLK_DUMMY(a57_clk, 250000000); static struct mux_clk gcc_debug_mux; static struct clk_ops clk_ops_debug_mux; static struct clk_mux_ops gcc_debug_mux_ops; Loading Loading @@ -2773,6 +2777,9 @@ static struct clk_lookup msm_clocks_gcc_8994[] = { CLK_LIST(gcc_usb_hs_ahb_clk), CLK_LIST(gcc_usb_hs_system_clk), CLK_LIST(gcc_usb_phy_cfg_ahb2phy_clk), CLK_LIST(cci_clk), CLK_LIST(a53_clk), CLK_LIST(a57_clk), }; static int msm_gcc_8994_probe(struct platform_device *pdev) Loading
include/dt-bindings/clock/msm-clocks-8994.h +5 −0 Original line number Diff line number Diff line Loading @@ -384,6 +384,11 @@ #define clk_mdss_pclk0_clk 0x3487234a #define clk_mdss_pclk1_clk 0xd5804246 /* clock_cpu controlled clocks */ #define clk_cci_clk 0x96854074 #define clk_a53_clk 0x5c9f8836 #define clk_a57_clk 0x6c7dc3ea /* clock_debug controlled clocks */ #define clk_gcc_debug_mux 0x8121ac15 Loading