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Commit 681ad3d2 authored by Kumar Gala's avatar Kumar Gala
Browse files

msm: pcie: Rename "qti" device tree prefix back to "qcom" 



Rename properties and compatible strings to return to the old
naming convention.

Change-Id: Idb46b85500d0458897e88dcb96d0a778d1b8a021
Signed-off-by: default avatarKumar Gala <galak@codeaurora.org>
parent 058bbf4e

Documentation/devicetree/bindings/pci/msm_pcie.txt

+12 −12
Original line number Diff line number Diff line
@@ -3,9 +3,9 @@ MSM PCIe 
MSM PCI express root complex



Required properties:

  - compatible: should be "qti,msm-pcie"

  - compatible: should be "qcom,msm-pcie"

  - cell-index: defines root complex ID.

  - qti,ctrl-amt: Number of controllers.

  - qcom,ctrl-amt: Number of controllers.

  - #address-cells: Should provide a value of 0.

  - reg: should contain PCIe register maps.

  - reg-names: indicates various resources passed to driver by name.
@@ -36,7 +36,7 @@ Required properties: 
    vreg-0.9-supply: phandle to the analog supply for the PCIe controller.



Optional Properties:

  - qti,<supply-name>-voltage-level: specifies voltage levels for supply.

  - qcom,<supply-name>-voltage-level: specifies voltage levels for supply.

    Should be specified in pairs (max, min, optimal), units uV.

  - clock-names: list of names of clock inputs.

		     Should be "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
@@ -45,18 +45,18 @@ Optional Properties: 
				"pcie_0_ldo";

  - max-clock-frequency-hz: list of the maximum operating frequencies stored

				in the same order of clock names;

  - qti,l1ss-supported: L1 sub-states (L1ss) is supported.

  - qti,aux-clk-sync: The AUX clock is synchronous to the Core clock to

  - qcom,l1ss-supported: L1 sub-states (L1ss) is supported.

  - qcom,aux-clk-sync: The AUX clock is synchronous to the Core clock to

    support L1ss.

  - qcom,msi-gicm-addr: MSI address for GICv2m.

  - qcom,msi-gicm-base: MSI IRQ base for GICv2m.



Example:



	pcie0: qti,pcie@fc520000 {

		compatible = "qti,msm_pcie";

	pcie0: qcom,pcie@fc520000 {

		compatible = "qcom,msm_pcie";

		cell-index = <0>;

		qti,ctrl-amt = <1>;

		qcom,ctrl-amt = <1>;

		#address-cells = <0>;

		reg = <0xfc520000 0x2000>,

		      <0xfc526000 0x1000>,
@@ -98,8 +98,8 @@ Example: 
		vreg-0.9-supply = <&pma8084_l4>;

		vreg-3.3-supply = <&wlan_vreg>;



		qti,vreg-1.8-voltage-level = <1800000 1800000 1000>;

		qti,vreg-0.9-voltage-level = <950000 950000 24000>;

		qcom,vreg-1.8-voltage-level = <1800000 1800000 1000>;

		qcom,vreg-0.9-voltage-level = <950000 950000 24000>;



		clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",

				"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
@@ -107,8 +107,8 @@ Example: 
				"pcie_0_ldo";

		max-clock-frequency-hz = <125000000>, <0>, <1000000>,

						<0>, <0>, <0>, <0>;

		qti,l1ss-supported;

		qti,aux-clk-sync;

		qcom,l1ss-supported;

		qcom,aux-clk-sync;

		qcom,msi-gicm-addr = <0xf9040040>;

		qcom,msi-gicm-base = <0x160>;

	};

arch/arm/boot/dts/qti/apq8084.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -451,10 +451,10 @@ 
		qcom,pipe-attr-ee;

	};



	pcie0: qti,pcie@fc520000 {

		compatible = "qti,msm_pcie";

	pcie0: qcom,pcie@fc520000 {

		compatible = "qcom,msm_pcie";

		cell-index = <0>;

		qti,ctrl-amt = <1>;

		qcom,ctrl-amt = <1>;



		reg = <0xfc520000 0x2000>,

		      <0xfc526000 0x1000>,
@@ -500,7 +500,7 @@ 
		vreg-0.9-supply = <&pma8084_l4>;

		vreg-3.3-supply = <&wlan_vreg>;



		qti,l1ss-supported;

		qcom,l1ss-supported;



		qcom,msi-gicm-addr = <0xf9040040>;

		qcom,msi-gicm-base = <0x160>;

arch/arm/boot/dts/qti/fsm9900.dtsi

+8 −8
Original line number Diff line number Diff line
@@ -1078,10 +1078,10 @@ 
		qcom,android-usb-swfi-latency = <1>;

	};



	pcie0: qti,pcie@fc520000 {

		compatible = "qti,msm_pcie";

	pcie0: qcom,pcie@fc520000 {

		compatible = "qcom,msm_pcie";

		cell-index = <0>;

		qti,ctrl-amt = <1>;

		qcom,ctrl-amt = <1>;



		reg = <0xfc520000 0x2000>,

		      <0xfc526000 0x1000>,
@@ -1126,7 +1126,7 @@ 
		vreg-1.8-supply = <&pma8084_l12>;

		vreg-0.9-supply = <&pma8084_l3>;

		vreg-3.3-supply = <&pcie0_power_en_vreg>;

		qti,vreg-0.9-voltage-level = <950000 950000 24000>;

		qcom,vreg-0.9-voltage-level = <950000 950000 24000>;



		clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",

				"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
@@ -1136,11 +1136,11 @@ 
						<0>, <0>, <0>, <0>;

	};



	pcie1: qti,pcie@fc528000 {

	pcie1: qcom,pcie@fc528000 {

		status = "disabled";

		compatible = "qti,msm_pcie";

		compatible = "qcom,msm_pcie";

		cell-index = <1>;

		qti,ctrl-amt = <1>;

		qcom,ctrl-amt = <1>;



		reg = <0xfc528000 0x2000>,

		      <0xfc52e000 0x1000>,
@@ -1185,7 +1185,7 @@ 
		vreg-1.8-supply = <&pma8084_l12>;

		vreg-0.9-supply = <&pma8084_l3>;

		vreg-3.3-supply = <&pcie1_power_en_vreg>;

		qti,vreg-0.9-voltage-level = <950000 950000 24000>;

		qcom,vreg-0.9-voltage-level = <950000 950000 24000>;



		clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src",

				"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",

arch/arm/boot/dts/qti/msmkrypton.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -210,10 +210,10 @@ 
		interrupts = <0 94 0>;

	};



	pcie0: qti,pcie@fc520000 {

		compatible = "qti,msm_pcie";

	pcie0: qcom,pcie@fc520000 {

		compatible = "qcom,msm_pcie";

		cell-index = <0>;

		qti,ctrl-amt = <1>;

		qcom,ctrl-amt = <1>;



		reg = <0xfc520000 0x2000>,

		      <0xfc526000 0x1000>,
@@ -257,8 +257,8 @@ 
		vreg-1.8-supply = <&pmd9635_l8>;

		vreg-0.9-supply = <&pmd9635_l4>;



		qti,vreg-1.8-voltage-level = <1800000 1800000 1000>;

		qti,vreg-0.9-voltage-level = <950000 950000 24000>;

		qcom,vreg-1.8-voltage-level = <1800000 1800000 1000>;

		qcom,vreg-0.9-voltage-level = <950000 950000 24000>;



		clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",

				"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",

arch/arm/mach-msm/board-8084.c

+2 −2
Original line number Diff line number Diff line
@@ -46,8 +46,8 @@ static struct of_dev_auxdata apq8084_auxdata_lookup[] __initdata = { 
	OF_DEV_AUXDATA("qca,qca1530", 0x00000000, "qca1530.1", NULL),

	OF_DEV_AUXDATA("qcom,ufshc", 0xFC594000, "msm_ufs.1", NULL),

	OF_DEV_AUXDATA("qcom,xhci-msm-hsic", 0xf9c00000, "msm_hsic_host", NULL),

	OF_DEV_AUXDATA("qti,msm_pcie", 0xFC520000, "msm_pcie.1", NULL),

	OF_DEV_AUXDATA("qti,msm_pcie", 0xFC528000, "msm_pcie.2", NULL),

	OF_DEV_AUXDATA("qcom,msm_pcie", 0xFC520000, "msm_pcie.1", NULL),

	OF_DEV_AUXDATA("qcom,msm_pcie", 0xFC528000, "msm_pcie.2", NULL),

	{}

};