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Commit 680da876 authored by Jesse Barnes's avatar Jesse Barnes Committed by Keith Packard
Browse files

drm/i915: enable cacheable objects on Ivybridge 



IVB supports these bits as well.

Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
parent 4b9de737

drivers/gpu/drm/i915/i915_gem.c

+1 −1
Original line number Diff line number Diff line
@@ -3613,7 +3613,7 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 
	obj->base.write_domain = I915_GEM_DOMAIN_CPU;

	obj->base.read_domains = I915_GEM_DOMAIN_CPU;



	if (IS_GEN6(dev)) {

	if (IS_GEN6(dev) || IS_GEN7(dev)) {

		/* On Gen6, we can have the GPU use the LLC (the CPU

		 * cache) for about a 10% performance improvement

		 * compared to uncached.  Graphics requests other than