Loading drivers/video/msm/mdss/mdss_mdp_ctl.c +29 −2 Original line number Diff line number Diff line Loading @@ -2250,7 +2250,8 @@ static void mdss_mdp_mixer_setup(struct mdss_mdp_ctl *master_ctl, int i; int stage, screen_state, outsize; u32 off, blend_op, blend_stage, mpq_num; u32 mixercfg = 0, mixer_op_mode = 0, bg_alpha_enable = 0; u32 mixercfg = 0, mixer_op_mode = 0, bg_alpha_enable = 0, mixercfg_extn = 0; u32 fg_alpha = 0, bg_alpha = 0; struct mdss_mdp_pipe *pipe; struct mdss_mdp_ctl *ctl = NULL; Loading Loading @@ -2318,6 +2319,12 @@ static void mdss_mdp_mixer_setup(struct mdss_mdp_ctl *master_ctl, blend_stage = stage - MDSS_MDP_STAGE_0; off = MDSS_MDP_REG_LM_BLEND_OFFSET(blend_stage); /* * Account for additional blending stages * from MDP v1.5 onwards */ if (blend_stage > 3) off += MDSS_MDP_REG_LM_BLEND_STAGE4; blend_op = (MDSS_MDP_BLEND_FG_ALPHA_FG_CONST | MDSS_MDP_BLEND_BG_ALPHA_BG_CONST); fg_alpha = pipe->alpha; Loading Loading @@ -2389,8 +2396,25 @@ static void mdss_mdp_mixer_setup(struct mdss_mdp_ctl *master_ctl, pipe->num == MDSS_MDP_SSPP_RGB3) { /* Add 2 to account for Cursor & Border bits */ mixercfg |= stage << ((3 * pipe->num)+2); } else { } else if (stage < MDSS_MDP_STAGE_6) { mixercfg |= stage << (3 * pipe->num); } else { /* * The ctl layer extension bits are ordered * VIG0-3, RGB0-3, DMA0-1 */ if (pipe->num < MDSS_MDP_SSPP_RGB0) mixercfg_extn |= BIT(pipe->num << 1); else if (pipe->num >= MDSS_MDP_SSPP_RGB0 && pipe->num < MDSS_MDP_SSPP_DMA0) mixercfg_extn |= BIT((pipe->num + 1) << 1); else if (pipe->num >= MDSS_MDP_SSPP_DMA0 && pipe->num < MDSS_MDP_SSPP_VIG3) mixercfg_extn |= BIT((pipe->num + 2) << 1); else if (pipe->num == MDSS_MDP_SSPP_VIG3) mixercfg_extn |= BIT(6); else mixercfg_extn |= BIT(14); } trace_mdp_sspp_change(pipe); Loading Loading @@ -2427,6 +2451,9 @@ update_mixer: mdp_mixer_write(mixer, MDSS_MDP_REG_LM_OP_MODE, mixer_op_mode); off = __mdss_mdp_ctl_get_mixer_off(mixer); mdss_mdp_ctl_write(ctl, off, mixercfg); /* Program ctl layer extension bits */ mdss_mdp_ctl_write(ctl, off + MDSS_MDP_REG_CTL_LAYER_EXTN_OFFSET, mixercfg_extn); } int mdss_mdp_mixer_addr_setup(struct mdss_data_type *mdata, Loading drivers/video/msm/mdss/mdss_mdp_hwio.h +5 −0 Original line number Diff line number Diff line Loading @@ -132,6 +132,7 @@ enum mdss_mdp_ctl_index { #define MDSS_MDP_REG_CTL_START 0x01C #define MDSS_MDP_REG_CTL_PACK_3D 0x020 #define MDSS_MDP_REG_CTL_SW_RESET 0x030 #define MDSS_MDP_REG_CTL_LAYER_EXTN_OFFSET 0x40 #define MDSS_MDP_CTL_OP_VIDEO_MODE (0 << 17) #define MDSS_MDP_CTL_OP_CMD_MODE (1 << 17) Loading Loading @@ -302,6 +303,9 @@ enum mdss_mdp_stage_index { MDSS_MDP_STAGE_1, MDSS_MDP_STAGE_2, MDSS_MDP_STAGE_3, MDSS_MDP_STAGE_4, MDSS_MDP_STAGE_5, MDSS_MDP_STAGE_6, MDSS_MDP_MAX_STAGE }; #define MAX_PIPES_PER_STAGE 0x2 Loading @@ -324,6 +328,7 @@ enum mdss_mdp_stage_index { #define MDSS_MDP_REG_LM_BLEND_BG_TRANSP_LOW1 0x20 #define MDSS_MDP_REG_LM_BLEND_BG_TRANSP_HIGH0 0x24 #define MDSS_MDP_REG_LM_BLEND_BG_TRANSP_HIGH1 0x28 #define MDSS_MDP_REG_LM_BLEND_STAGE4 0x150 #define MDSS_MDP_REG_LM_CURSOR_IMG_SIZE 0xE0 #define MDSS_MDP_REG_LM_CURSOR_SIZE 0xE4 Loading drivers/video/msm/mdss/mdss_mdp_overlay.c +14 −2 Original line number Diff line number Diff line Loading @@ -57,7 +57,8 @@ static int mdss_mdp_overlay_free_fb_pipe(struct msm_fb_data_type *mfd); static int mdss_mdp_overlay_fb_parse_dt(struct msm_fb_data_type *mfd); static int mdss_mdp_overlay_off(struct msm_fb_data_type *mfd); static void __overlay_kickoff_requeue(struct msm_fb_data_type *mfd); static int __mdss_mdp_overlay_check_zorder(struct mdss_data_type *mdata, struct mdp_overlay *req); static inline bool is_ov_right_blend(struct mdp_rect *left_blend, struct mdp_rect *right_blend, u32 left_lm_w) { Loading Loading @@ -266,7 +267,7 @@ int mdss_mdp_overlay_req_check(struct msm_fb_data_type *mfd, min_dst_size = 2; } if (req->z_order >= MDSS_MDP_MAX_STAGE) { if (__mdss_mdp_overlay_check_zorder(mdata, req)) { pr_err("zorder %d out of range\n", req->z_order); return -ERANGE; } Loading Loading @@ -401,6 +402,17 @@ int mdss_mdp_overlay_req_check(struct msm_fb_data_type *mfd, return 0; } static int __mdss_mdp_overlay_check_zorder(struct mdss_data_type *mdata, struct mdp_overlay *req) { int max_target_zorder = MDSS_MDP_STAGE_4; switch (mdata->mdp_rev) { case MDSS_MDP_HW_REV_105: max_target_zorder = MDSS_MDP_MAX_STAGE; break; } return (req->z_order >= max_target_zorder) ? -EINVAL : 0; } static int __mdp_pipe_tune_perf(struct mdss_mdp_pipe *pipe, bool is_single_layer) { Loading include/uapi/linux/msm_mdp.h +1 −1 Original line number Diff line number Diff line Loading @@ -1094,7 +1094,7 @@ struct mdp_mixer_info { int z_order; }; #define MAX_PIPE_PER_MIXER 4 #define MAX_PIPE_PER_MIXER 7 struct msmfb_mixer_info_req { int mixer_num; Loading Loading
drivers/video/msm/mdss/mdss_mdp_ctl.c +29 −2 Original line number Diff line number Diff line Loading @@ -2250,7 +2250,8 @@ static void mdss_mdp_mixer_setup(struct mdss_mdp_ctl *master_ctl, int i; int stage, screen_state, outsize; u32 off, blend_op, blend_stage, mpq_num; u32 mixercfg = 0, mixer_op_mode = 0, bg_alpha_enable = 0; u32 mixercfg = 0, mixer_op_mode = 0, bg_alpha_enable = 0, mixercfg_extn = 0; u32 fg_alpha = 0, bg_alpha = 0; struct mdss_mdp_pipe *pipe; struct mdss_mdp_ctl *ctl = NULL; Loading Loading @@ -2318,6 +2319,12 @@ static void mdss_mdp_mixer_setup(struct mdss_mdp_ctl *master_ctl, blend_stage = stage - MDSS_MDP_STAGE_0; off = MDSS_MDP_REG_LM_BLEND_OFFSET(blend_stage); /* * Account for additional blending stages * from MDP v1.5 onwards */ if (blend_stage > 3) off += MDSS_MDP_REG_LM_BLEND_STAGE4; blend_op = (MDSS_MDP_BLEND_FG_ALPHA_FG_CONST | MDSS_MDP_BLEND_BG_ALPHA_BG_CONST); fg_alpha = pipe->alpha; Loading Loading @@ -2389,8 +2396,25 @@ static void mdss_mdp_mixer_setup(struct mdss_mdp_ctl *master_ctl, pipe->num == MDSS_MDP_SSPP_RGB3) { /* Add 2 to account for Cursor & Border bits */ mixercfg |= stage << ((3 * pipe->num)+2); } else { } else if (stage < MDSS_MDP_STAGE_6) { mixercfg |= stage << (3 * pipe->num); } else { /* * The ctl layer extension bits are ordered * VIG0-3, RGB0-3, DMA0-1 */ if (pipe->num < MDSS_MDP_SSPP_RGB0) mixercfg_extn |= BIT(pipe->num << 1); else if (pipe->num >= MDSS_MDP_SSPP_RGB0 && pipe->num < MDSS_MDP_SSPP_DMA0) mixercfg_extn |= BIT((pipe->num + 1) << 1); else if (pipe->num >= MDSS_MDP_SSPP_DMA0 && pipe->num < MDSS_MDP_SSPP_VIG3) mixercfg_extn |= BIT((pipe->num + 2) << 1); else if (pipe->num == MDSS_MDP_SSPP_VIG3) mixercfg_extn |= BIT(6); else mixercfg_extn |= BIT(14); } trace_mdp_sspp_change(pipe); Loading Loading @@ -2427,6 +2451,9 @@ update_mixer: mdp_mixer_write(mixer, MDSS_MDP_REG_LM_OP_MODE, mixer_op_mode); off = __mdss_mdp_ctl_get_mixer_off(mixer); mdss_mdp_ctl_write(ctl, off, mixercfg); /* Program ctl layer extension bits */ mdss_mdp_ctl_write(ctl, off + MDSS_MDP_REG_CTL_LAYER_EXTN_OFFSET, mixercfg_extn); } int mdss_mdp_mixer_addr_setup(struct mdss_data_type *mdata, Loading
drivers/video/msm/mdss/mdss_mdp_hwio.h +5 −0 Original line number Diff line number Diff line Loading @@ -132,6 +132,7 @@ enum mdss_mdp_ctl_index { #define MDSS_MDP_REG_CTL_START 0x01C #define MDSS_MDP_REG_CTL_PACK_3D 0x020 #define MDSS_MDP_REG_CTL_SW_RESET 0x030 #define MDSS_MDP_REG_CTL_LAYER_EXTN_OFFSET 0x40 #define MDSS_MDP_CTL_OP_VIDEO_MODE (0 << 17) #define MDSS_MDP_CTL_OP_CMD_MODE (1 << 17) Loading Loading @@ -302,6 +303,9 @@ enum mdss_mdp_stage_index { MDSS_MDP_STAGE_1, MDSS_MDP_STAGE_2, MDSS_MDP_STAGE_3, MDSS_MDP_STAGE_4, MDSS_MDP_STAGE_5, MDSS_MDP_STAGE_6, MDSS_MDP_MAX_STAGE }; #define MAX_PIPES_PER_STAGE 0x2 Loading @@ -324,6 +328,7 @@ enum mdss_mdp_stage_index { #define MDSS_MDP_REG_LM_BLEND_BG_TRANSP_LOW1 0x20 #define MDSS_MDP_REG_LM_BLEND_BG_TRANSP_HIGH0 0x24 #define MDSS_MDP_REG_LM_BLEND_BG_TRANSP_HIGH1 0x28 #define MDSS_MDP_REG_LM_BLEND_STAGE4 0x150 #define MDSS_MDP_REG_LM_CURSOR_IMG_SIZE 0xE0 #define MDSS_MDP_REG_LM_CURSOR_SIZE 0xE4 Loading
drivers/video/msm/mdss/mdss_mdp_overlay.c +14 −2 Original line number Diff line number Diff line Loading @@ -57,7 +57,8 @@ static int mdss_mdp_overlay_free_fb_pipe(struct msm_fb_data_type *mfd); static int mdss_mdp_overlay_fb_parse_dt(struct msm_fb_data_type *mfd); static int mdss_mdp_overlay_off(struct msm_fb_data_type *mfd); static void __overlay_kickoff_requeue(struct msm_fb_data_type *mfd); static int __mdss_mdp_overlay_check_zorder(struct mdss_data_type *mdata, struct mdp_overlay *req); static inline bool is_ov_right_blend(struct mdp_rect *left_blend, struct mdp_rect *right_blend, u32 left_lm_w) { Loading Loading @@ -266,7 +267,7 @@ int mdss_mdp_overlay_req_check(struct msm_fb_data_type *mfd, min_dst_size = 2; } if (req->z_order >= MDSS_MDP_MAX_STAGE) { if (__mdss_mdp_overlay_check_zorder(mdata, req)) { pr_err("zorder %d out of range\n", req->z_order); return -ERANGE; } Loading Loading @@ -401,6 +402,17 @@ int mdss_mdp_overlay_req_check(struct msm_fb_data_type *mfd, return 0; } static int __mdss_mdp_overlay_check_zorder(struct mdss_data_type *mdata, struct mdp_overlay *req) { int max_target_zorder = MDSS_MDP_STAGE_4; switch (mdata->mdp_rev) { case MDSS_MDP_HW_REV_105: max_target_zorder = MDSS_MDP_MAX_STAGE; break; } return (req->z_order >= max_target_zorder) ? -EINVAL : 0; } static int __mdp_pipe_tune_perf(struct mdss_mdp_pipe *pipe, bool is_single_layer) { Loading
include/uapi/linux/msm_mdp.h +1 −1 Original line number Diff line number Diff line Loading @@ -1094,7 +1094,7 @@ struct mdp_mixer_info { int z_order; }; #define MAX_PIPE_PER_MIXER 4 #define MAX_PIPE_PER_MIXER 7 struct msmfb_mixer_info_req { int mixer_num; Loading