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Commit 65eb6b43 authored by Paolo Ciarrocchi's avatar Paolo Ciarrocchi Committed by Ingo Molnar
Browse files

x86: coding style fixes to arch/x86/kernel/cpu/intel.c 



Before:
   total: 37 errors, 16 warnings, 366 lines checked
After:
   total: 0 errors, 15 warnings, 369 lines checked

No code changed:

arch/x86/kernel/cpu/intel.o:

   text	   data	    bss	    dec	    hex	filename
   1534	    452	      0	   1986	    7c2	intel.o.before
   1534	    452	      0	   1986	    7c2	intel.o.after

md5:
   1ca348a06de6eb354c4b6ea715a57db5  intel.o.before.asm
   1ca348a06de6eb354c4b6ea715a57db5  intel.o.after.asm

Signed-off-by: default avatarPaolo Ciarrocchi <paolo.ciarrocchi@gmail.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 60e11746

arch/x86/kernel/cpu/intel.c

+43 −40
Original line number Diff line number Diff line
@@ -127,7 +127,7 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) 
	 */

	c->f00f_bug = 0;

	if (!paravirt_enabled() && c->x86 == 5) {

		static int f00f_workaround_enabled = 0;

		static int f00f_workaround_enabled;



		c->f00f_bug = 1;

		if (!f00f_workaround_enabled) {
@@ -150,9 +150,11 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) 
	if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)

		clear_bit(X86_FEATURE_SEP, c->x86_capability);



	/* Names for the Pentium II/Celeron processors 

	   detectable only by also checking the cache size.

	   Dixon is NOT a Celeron. */

	/*

	 * Names for the Pentium II/Celeron processors

	 * detectable only by also checking the cache size.

	 * Dixon is NOT a Celeron.

	 */

	if (c->x86 == 6) {

		switch (c->x86_model) {

		case 5:
@@ -228,7 +230,8 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) 


static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)

{

	/* Intel PIII Tualatin. This comes in two flavours.

	/*

	 * Intel PIII Tualatin. This comes in two flavours.

	 * One has 256kb of cache, the other 512. We have no way

	 * to determine which, so we use a boottime override

	 * for the 512kb model, and assume 256 otherwise.
@@ -361,5 +364,5 @@ unsigned long long cmpxchg_486_u64(volatile void *ptr, u64 old, u64 new) 
EXPORT_SYMBOL(cmpxchg_486_u64);

#endif



// arch_initcall(intel_cpu_init);

/* arch_initcall(intel_cpu_init); */