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Commit 6592fe64 authored by Xiaogang Cui's avatar Xiaogang Cui
Browse files

ARM: dts: msm: add dt support for etm save and restore for msmtellurium 



Add device tree entries for ETM save-restore across power collapse
using memory mapped access

Change-Id: I26973c50dcdd8664d1f90a9806acb19f511d4ff8
Signed-off-by: default avatarXiaogang Cui <xiaogang@codeaurora.org>
parent 5e498329

arch/arm/boot/dts/qcom/msmtellurium.dtsi

+110 −0
Original line number Diff line number Diff line
@@ -975,6 +975,116 @@ 
		qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;

		linux,contiguous-region = <&modem_mem>;

	};



	jtag_fuse: jtagfuse@5e01c {

		compatible = "qcom,jtag-fuse-v2";

		reg = <0x5e01c 0x8>;

		reg-names = "fuse-base";

	};



	jtag_mm0: jtagmm@8fc000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x8fc000 0x1000>,

		      <0x8f0000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU0>;



		clocks = <&clock_gcc clk_qdss_clk>,

		         <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	jtag_mm1: jtagmm@8fd000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x8fd000 0x1000>,

		      <0x8f2000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU1>;



		clocks = <&clock_gcc clk_qdss_clk>,

		         <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	jtag_mm2: jtagmm@8fe000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x8fe000 0x1000>,

		      <0x8f4000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU2>;



		clocks = <&clock_gcc clk_qdss_clk>,

		         <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	jtag_mm3: jtagmm@8ff000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x8ff000 0x1000>,

		      <0x8f6000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU3>;



		clocks = <&clock_gcc clk_qdss_clk>,

		         <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	jtag_mm4: jtagmm@8dc000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x8dc000 0x1000>,

		      <0x8d0000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU4>;



		clocks = <&clock_gcc clk_qdss_clk>,

		         <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	jtag_mm5: jtagmm@8dd000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x8dd000 0x1000>,

		      <0x8d2000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU5>;



		clocks = <&clock_gcc clk_qdss_clk>,

		         <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	jtag_mm6: jtagmm@8de000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x8de000 0x1000>,

		      <0x8d4000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU6>;



		clocks = <&clock_gcc clk_qdss_clk>,

		         <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	jtag_mm7: jtagmm@8df000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x8df000 0x1000>,

		      <0x8d6000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU7>;



		clocks = <&clock_gcc clk_qdss_clk>,

		         <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};

};



&gdsc_venus {