Loading Documentation/devicetree/bindings/usb/msm-phy.txt +6 −3 Original line number Diff line number Diff line Loading @@ -5,6 +5,8 @@ HSUSB PHY Required properties: - compatible: Should be "qcom,usb-hsphy" - reg: Address and length of the register set for the device Required regs are: "core" : the QSCRATCH base register set - <supply-name>-supply: phandle to the regulator device tree node Required "supply-name" examples are: "vdd" : vdd supply for HSPHY digital circuit operation Loading @@ -15,9 +17,10 @@ Required properties: microvolts or a value corresponding to voltage corner Optional properties: - reg: Address and length of the TCSR register to be written when performing a block reset, as well as to intialize the internal MUX to select the correct controller. If present this must be the second register listed. - reg: Additional registers "tcsr" : top-level CSR register to be written during power-on reset intialize the internal MUX that controls whether this PHY is used with the USB3 or the USB2 controller. - qcom,hsphy-init: Init value used to override HSPHY parameters into QSCRATCH register. This 32-bit value represents parameters as follows: Loading arch/arm/boot/dts/qcom/apq8084.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -4445,6 +4445,7 @@ compatible = "qcom,usb-hsphy"; reg = <0xf92f8800 0x3ff>, <0xfd4ab204 0x4>; reg-names = "core", "tcsr"; qcom,hsphy-init = <0x00D191A4>; vdd-supply = <&pma8084_s1>; vdda18-supply = <&pma8084_l6>; Loading @@ -4471,6 +4472,7 @@ hsphy1: hsphy@f94f8800 { compatible = "qcom,usb-hsphy"; reg = <0xf94f8800 0x3ff>; reg-names = "core"; qcom,hsphy-init = <0x00D191A4>; vdd-supply = <&pma8084_s1>; vdda18-supply = <&pma8084_l6>; Loading arch/arm/boot/dts/qcom/mdm9630.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -545,6 +545,7 @@ hsphy0: hsphy@f92f8800 { compatible = "qcom,usb-hsphy"; reg = <0xf92f8800 0x3ff>; reg-names = "core"; qcom,hsphy-init = <0x00D191A4>; vdd-supply = <&pmd9635_l3_corner>; vdda18-supply = <&pmd9635_l8>; Loading arch/arm/boot/dts/qcom/msm8974.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -1590,6 +1590,7 @@ hsphy: hsphy@f92f8800 { compatible = "qcom,usb-hsphy"; reg = <0xf92f8800 0x3ff>; reg-names = "core"; qcom,hsphy-init = <0x00D191A4>; vdd-supply = <&pm8841_s2_corner>; vdda18-supply = <&pm8941_l6>; Loading arch/arm/boot/dts/qcom/msm8994.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -1524,6 +1524,7 @@ compatible = "qcom,usb-hsphy"; status = "disabled"; reg = <0xf92f8800 0x3ff>; reg-names = "core"; qcom,hsphy-init = <0x00D191A4>; vdd-supply = <&pm8994_s2_corner>; vdda18-supply = <&pm8994_l6>; Loading Loading
Documentation/devicetree/bindings/usb/msm-phy.txt +6 −3 Original line number Diff line number Diff line Loading @@ -5,6 +5,8 @@ HSUSB PHY Required properties: - compatible: Should be "qcom,usb-hsphy" - reg: Address and length of the register set for the device Required regs are: "core" : the QSCRATCH base register set - <supply-name>-supply: phandle to the regulator device tree node Required "supply-name" examples are: "vdd" : vdd supply for HSPHY digital circuit operation Loading @@ -15,9 +17,10 @@ Required properties: microvolts or a value corresponding to voltage corner Optional properties: - reg: Address and length of the TCSR register to be written when performing a block reset, as well as to intialize the internal MUX to select the correct controller. If present this must be the second register listed. - reg: Additional registers "tcsr" : top-level CSR register to be written during power-on reset intialize the internal MUX that controls whether this PHY is used with the USB3 or the USB2 controller. - qcom,hsphy-init: Init value used to override HSPHY parameters into QSCRATCH register. This 32-bit value represents parameters as follows: Loading
arch/arm/boot/dts/qcom/apq8084.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -4445,6 +4445,7 @@ compatible = "qcom,usb-hsphy"; reg = <0xf92f8800 0x3ff>, <0xfd4ab204 0x4>; reg-names = "core", "tcsr"; qcom,hsphy-init = <0x00D191A4>; vdd-supply = <&pma8084_s1>; vdda18-supply = <&pma8084_l6>; Loading @@ -4471,6 +4472,7 @@ hsphy1: hsphy@f94f8800 { compatible = "qcom,usb-hsphy"; reg = <0xf94f8800 0x3ff>; reg-names = "core"; qcom,hsphy-init = <0x00D191A4>; vdd-supply = <&pma8084_s1>; vdda18-supply = <&pma8084_l6>; Loading
arch/arm/boot/dts/qcom/mdm9630.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -545,6 +545,7 @@ hsphy0: hsphy@f92f8800 { compatible = "qcom,usb-hsphy"; reg = <0xf92f8800 0x3ff>; reg-names = "core"; qcom,hsphy-init = <0x00D191A4>; vdd-supply = <&pmd9635_l3_corner>; vdda18-supply = <&pmd9635_l8>; Loading
arch/arm/boot/dts/qcom/msm8974.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -1590,6 +1590,7 @@ hsphy: hsphy@f92f8800 { compatible = "qcom,usb-hsphy"; reg = <0xf92f8800 0x3ff>; reg-names = "core"; qcom,hsphy-init = <0x00D191A4>; vdd-supply = <&pm8841_s2_corner>; vdda18-supply = <&pm8941_l6>; Loading
arch/arm/boot/dts/qcom/msm8994.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -1524,6 +1524,7 @@ compatible = "qcom,usb-hsphy"; status = "disabled"; reg = <0xf92f8800 0x3ff>; reg-names = "core"; qcom,hsphy-init = <0x00D191A4>; vdd-supply = <&pm8994_s2_corner>; vdda18-supply = <&pm8994_l6>; Loading