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Commit 64c9c7d1 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "coresight: make etm probe independent of core0"

parents 06592bc0 bb6f7a93

Documentation/devicetree/bindings/arm/msm/jtag-mm.txt

+4 −0
Original line number Diff line number Diff line
@@ -13,6 +13,8 @@ compatible: component name used for driver matching, should be: 
reg: physical base address and length of the register set

reg-names: should be "etm-base" for etm register set and "debug-base" for debug

	register set.

qcom,coresight-jtagmm-cpu : specifies phandle for the cpu associated with the

			    jtag-mm device



Example:

jtag_mm: jtagmm@fc332000 {
@@ -20,4 +22,6 @@ jtag_mm: jtagmm@fc332000 { 
	reg = <0xfc332000 0x1000>,

		<0xfc333000 0x1000>;

	reg-names = "etm-base","debug-base";



	qcom,coresight-jtagmm-cpu = <&CPU0>;

	};

Documentation/devicetree/bindings/coresight/coresight.txt

+3 −0
Original line number Diff line number Diff line
@@ -104,6 +104,7 @@ Required properties: 
- coresight-name : unique descriptive name of the component

- coresight-nr-inports : number of input ports on the component

- coresight-cti-cpu : cpu phandle for cpu cti, required when qcom,cti-save is true

- coresight-etm-cpu : specifies phandle for the cpu associated with the ETM device



coresight-outports, coresight-child-list and coresight-child-ports lists will

be of the same length and will have a one to one correspondence among the
@@ -278,6 +279,8 @@ Examples: 
		coresight-outports = <0>;

		coresight-child-list = <&funnel_kpss>;

		coresight-child-ports = <0>;

		coresight-etm-cpu = <&CPU0>;



		qcom,pc-save;

		qcom,round-robin;

	};

arch/arm/boot/dts/qcom/apq8084-coresight.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -170,6 +170,7 @@ 
		coresight-outports = <0>;

		coresight-child-list = <&funnel_kpss>;

		coresight-child-ports = <0>;

		coresight-etm-cpu = <&CPU0>;



		qcom,pc-save;

		qcom,round-robin;
@@ -186,6 +187,7 @@ 
		coresight-outports = <0>;

		coresight-child-list = <&funnel_kpss>;

		coresight-child-ports = <1>;

		coresight-etm-cpu = <&CPU1>;



		qcom,pc-save;

		qcom,round-robin;
@@ -202,6 +204,7 @@ 
		coresight-outports = <0>;

		coresight-child-list = <&funnel_kpss>;

		coresight-child-ports = <2>;

		coresight-etm-cpu = <&CPU2>;



		qcom,pc-save;

		qcom,round-robin;
@@ -218,6 +221,7 @@ 
		coresight-outports = <0>;

		coresight-child-list = <&funnel_kpss>;

		coresight-child-ports = <3>;

		coresight-etm-cpu = <&CPU3>;



		qcom,pc-save;

		qcom,round-robin;

arch/arm/boot/dts/qcom/mdm9630-coresight.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -132,6 +132,7 @@ 
		coresight-outports = <0>;

		coresight-child-list = <&funnel_in1>;

		coresight-child-ports = <2>;

		coresight-etm-cpu = <&CPU0>;



		qcom,round-robin;

	};

arch/arm/boot/dts/qcom/mdm9630.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -425,6 +425,8 @@ 
		reg = <0xfc342000 0x1000>,

		      <0xfc340000 0x1000>;

		reg-names = "etm-base","debug-base";



		qcom,coresight-jtagmm-cpu = <&CPU0>;

	};



	qcom,msm-rtb {