Loading arch/arm/mach-msm/clock-gcc-8974.c +7 −13 Original line number Diff line number Diff line Loading @@ -1117,8 +1117,8 @@ static struct rcg_clk pdm2_clk_src = { }, }; /* This table is for MSM8974Pro AC SDCC1 */ static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk_ac[] = { /* For MSM8974Pro SDCC1 */ static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk_pro[] = { F( 144000, cxo, 16, 3, 25), F( 400000, cxo, 12, 1, 4), F( 20000000, gpll0, 15, 1, 2), Loading @@ -1130,11 +1130,7 @@ static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk_ac[] = { F_END }; /* * This table is for: * 1) SDCC[1-4] on MSM8974Pro AB, MSM8974 v2 and before * 2) SDCC[2-4] on MSM8974Pro AC */ /* For SDCC1 on MSM8974 v2 and SDCC[2-4] on all MSM8974 */ static struct clk_freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = { F( 144000, cxo, 16, 3, 25), F( 400000, cxo, 12, 1, 4), Loading Loading @@ -2552,7 +2548,7 @@ void msm8974_v2_clock_override(void) qup_i2c_clks[i][0]->parent = qup_i2c_clks[i][1]; } /* v2 to v3 clock changes */ /* v2 to Pro clock changes */ void msm8974_pro_clock_override(bool ac) { ce1_clk_src.c.fmax[VDD_DIG_LOW] = 75000000; Loading @@ -2562,11 +2558,9 @@ void msm8974_pro_clock_override(bool ac) ce2_clk_src.c.fmax[VDD_DIG_NOMINAL] = 150000000; ce2_clk_src.freq_tbl = ftbl_gcc_ce2_pro_clk; if (ac) { sdcc1_apps_clk_src.c.fmax[VDD_DIG_LOW] = 200000000; sdcc1_apps_clk_src.c.fmax[VDD_DIG_NOMINAL] = 400000000; sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_ac; } sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_pro; } static struct of_device_id msm_clock_gcc_match_table[] = { Loading Loading
arch/arm/mach-msm/clock-gcc-8974.c +7 −13 Original line number Diff line number Diff line Loading @@ -1117,8 +1117,8 @@ static struct rcg_clk pdm2_clk_src = { }, }; /* This table is for MSM8974Pro AC SDCC1 */ static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk_ac[] = { /* For MSM8974Pro SDCC1 */ static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk_pro[] = { F( 144000, cxo, 16, 3, 25), F( 400000, cxo, 12, 1, 4), F( 20000000, gpll0, 15, 1, 2), Loading @@ -1130,11 +1130,7 @@ static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk_ac[] = { F_END }; /* * This table is for: * 1) SDCC[1-4] on MSM8974Pro AB, MSM8974 v2 and before * 2) SDCC[2-4] on MSM8974Pro AC */ /* For SDCC1 on MSM8974 v2 and SDCC[2-4] on all MSM8974 */ static struct clk_freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = { F( 144000, cxo, 16, 3, 25), F( 400000, cxo, 12, 1, 4), Loading Loading @@ -2552,7 +2548,7 @@ void msm8974_v2_clock_override(void) qup_i2c_clks[i][0]->parent = qup_i2c_clks[i][1]; } /* v2 to v3 clock changes */ /* v2 to Pro clock changes */ void msm8974_pro_clock_override(bool ac) { ce1_clk_src.c.fmax[VDD_DIG_LOW] = 75000000; Loading @@ -2562,11 +2558,9 @@ void msm8974_pro_clock_override(bool ac) ce2_clk_src.c.fmax[VDD_DIG_NOMINAL] = 150000000; ce2_clk_src.freq_tbl = ftbl_gcc_ce2_pro_clk; if (ac) { sdcc1_apps_clk_src.c.fmax[VDD_DIG_LOW] = 200000000; sdcc1_apps_clk_src.c.fmax[VDD_DIG_NOMINAL] = 400000000; sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_ac; } sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_pro; } static struct of_device_id msm_clock_gcc_match_table[] = { Loading