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Commit 63a0ab6f authored by Pratik Patel's avatar Pratik Patel Committed by Stephen Boyd
Browse files

coresight: rename variables and functions from cs to coresight 



Complete the rename by changing cs to coresight for variables,
functions and constants.

Change-Id: I506d5872e5c09f201c4f3674d7722d36eca26921
Signed-off-by: default avatarPratik Patel <pratikp@codeaurora.org>
parent 30700919

drivers/coresight/coresight-etb.c

+3 −3
Original line number Diff line number Diff line
@@ -58,11 +58,11 @@ 
#define ETB_LOCK()							\

do {									\

	mb();								\

	etb_writel(drvdata, 0x0, CS_LAR);				\

	etb_writel(drvdata, 0x0, CORESIGHT_LAR);			\

} while (0)

#define ETB_UNLOCK()							\

do {									\

	etb_writel(drvdata, CS_UNLOCK_MAGIC, CS_LAR);			\

	etb_writel(drvdata, CORESIGHT_UNLOCK, CORESIGHT_LAR);		\

	mb();								\

} while (0)
@@ -372,7 +372,7 @@ static int etb_probe(struct platform_device *pdev) 
		goto err_clk_get;

	}



	ret = clk_set_rate(drvdata->clk, CS_CLK_RATE_TRACE);

	ret = clk_set_rate(drvdata->clk, CORESIGHT_CLK_RATE_TRACE);

	if (ret)

		goto err_clk_rate;

drivers/coresight/coresight-etm.c

+3 −3
Original line number Diff line number Diff line
@@ -130,11 +130,11 @@ enum { 
#define ETM_LOCK(cpu)							\

do {									\

	mb();								\

	etm_writel(drvdata, cpu, 0x0, CS_LAR);				\

	etm_writel(drvdata, cpu, 0x0, CORESIGHT_LAR);			\

} while (0)

#define ETM_UNLOCK(cpu)							\

do {									\

	etm_writel(drvdata, cpu, CS_UNLOCK_MAGIC, CS_LAR);		\

	etm_writel(drvdata, cpu, CORESIGHT_UNLOCK, CORESIGHT_LAR);	\

	mb();								\

} while (0)
@@ -1549,7 +1549,7 @@ static int etm_probe(struct platform_device *pdev) 
		goto err_clk_get;

	}



	ret = clk_set_rate(drvdata->clk, CS_CLK_RATE_TRACE);

	ret = clk_set_rate(drvdata->clk, CORESIGHT_CLK_RATE_TRACE);

	if (ret)

		goto err_clk_rate;

drivers/coresight/coresight-funnel.c

+3 −3
Original line number Diff line number Diff line
@@ -40,11 +40,11 @@ 
#define FUNNEL_LOCK(id)							\

do {									\

	mb();								\

	funnel_writel(drvdata, id, 0x0, CS_LAR);			\

	funnel_writel(drvdata, id, 0x0, CORESIGHT_LAR);			\

} while (0)

#define FUNNEL_UNLOCK(id)						\

do {									\

	funnel_writel(drvdata, id, CS_UNLOCK_MAGIC, CS_LAR);		\

	funnel_writel(drvdata, id, CORESIGHT_UNLOCK, CORESIGHT_LAR);	\

	mb();								\

} while (0)
@@ -209,7 +209,7 @@ static int funnel_probe(struct platform_device *pdev) 
		goto err_clk_get;

	}



	ret = clk_set_rate(drvdata->clk, CS_CLK_RATE_TRACE);

	ret = clk_set_rate(drvdata->clk, CORESIGHT_CLK_RATE_TRACE);

	if (ret)

		goto err_clk_rate;

drivers/coresight/coresight-priv.h

+12 −12
Original line number Diff line number Diff line
@@ -10,8 +10,8 @@ 
 * GNU General Public License for more details.

 */



#ifndef _CS_PRIV_H

#define _CS_PRIV_H

#ifndef _CORESIGHT_PRIV_H

#define _CORESIGHT_PRIV_H



#include <linux/bitops.h>
@@ -19,16 +19,16 @@ 
 * 0xFA0 - 0xFA4: Management	registers in PFTv1.0

 *		  Trace		registers in PFTv1.1

 */

#define CS_ITCTRL		(0xF00)

#define CS_CLAIMSET		(0xFA0)

#define CS_CLAIMCLR		(0xFA4)

#define CS_LAR			(0xFB0)

#define CS_LSR			(0xFB4)

#define CS_AUTHSTATUS		(0xFB8)

#define CS_DEVID		(0xFC8)

#define CS_DEVTYPE		(0xFCC)



#define CS_UNLOCK_MAGIC		(0xC5ACCE55)

#define CORESIGHT_ITCTRL	(0xF00)

#define CORESIGHT_CLAIMSET	(0xFA0)

#define CORESIGHT_CLAIMCLR	(0xFA4)

#define CORESIGHT_LAR		(0xFB0)

#define CORESIGHT_LSR		(0xFB4)

#define CORESIGHT_AUTHSTATUS	(0xFB8)

#define CORESIGHT_DEVID		(0xFC8)

#define CORESIGHT_DEVTYPE	(0xFCC)



#define CORESIGHT_UNLOCK	(0xC5ACCE55)



#define TIMEOUT_US		(100)

drivers/coresight/coresight-stm.c

+4 −4
Original line number Diff line number Diff line
@@ -59,11 +59,11 @@ enum { 
#define STM_LOCK()							\

do {									\

	mb();								\

	stm_writel(drvdata, 0x0, CS_LAR);				\

	stm_writel(drvdata, 0x0, CORESIGHT_LAR);			\

} while (0)

#define STM_UNLOCK()							\

do {									\

	stm_writel(drvdata, CS_UNLOCK_MAGIC, CS_LAR);			\

	stm_writel(drvdata, CORESIGHT_UNLOCK, CORESIGHT_LAR);		\

	mb();								\

} while (0)
@@ -551,7 +551,7 @@ static int stm_probe(struct platform_device *pdev) 
		goto err_clk_get;

	}



	ret = clk_set_rate(drvdata->clk, CS_CLK_RATE_TRACE);

	ret = clk_set_rate(drvdata->clk, CORESIGHT_CLK_RATE_TRACE);

	if (ret)

		goto err_clk_rate;