Merge branches 'dma40', 'pl08x', 'fsldma', 'imx' and 'intel-mid' into dmaengine

#define imx_has_dma_v1()	(cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())

#include <mach/dma.h>

#define IMX_DMA_CHANNELS  16

#define DMA_MODE_READ		0

void imx_dma_free(int channel);

enum imx_dma_prio {

	DMA_PRIO_HIGH = 0,

	DMA_PRIO_MEDIUM = 1,

	DMA_PRIO_LOW = 2

};

int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);

#endif	/* __MACH_DMA_V1_H__ */

/*

 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

#ifndef __ASM_ARCH_MXC_DMA_H__

#define __ASM_ARCH_MXC_DMA_H__

#include <linux/scatterlist.h>

#include <linux/device.h>

#include <linux/dmaengine.h>

/*

 * This enumerates peripheral types. Used for SDMA.

 */

enum sdma_peripheral_type {

	IMX_DMATYPE_SSI,	/* MCU domain SSI */

	IMX_DMATYPE_SSI_SP,	/* Shared SSI */

	IMX_DMATYPE_MMC,	/* MMC */

	IMX_DMATYPE_SDHC,	/* SDHC */

	IMX_DMATYPE_UART,	/* MCU domain UART */

	IMX_DMATYPE_UART_SP,	/* Shared UART */

	IMX_DMATYPE_FIRI,	/* FIRI */

	IMX_DMATYPE_CSPI,	/* MCU domain CSPI */

	IMX_DMATYPE_CSPI_SP,	/* Shared CSPI */

	IMX_DMATYPE_SIM,	/* SIM */

	IMX_DMATYPE_ATA,	/* ATA */

	IMX_DMATYPE_CCM,	/* CCM */

	IMX_DMATYPE_EXT,	/* External peripheral */

	IMX_DMATYPE_MSHC,	/* Memory Stick Host Controller */

	IMX_DMATYPE_MSHC_SP,	/* Shared Memory Stick Host Controller */

	IMX_DMATYPE_DSP,	/* DSP */

	IMX_DMATYPE_MEMORY,	/* Memory */

	IMX_DMATYPE_FIFO_MEMORY,/* FIFO type Memory */

	IMX_DMATYPE_SPDIF,	/* SPDIF */

	IMX_DMATYPE_IPU_MEMORY,	/* IPU Memory */

	IMX_DMATYPE_ASRC,	/* ASRC */

	IMX_DMATYPE_ESAI,	/* ESAI */

};

enum imx_dma_prio {

	DMA_PRIO_HIGH = 0,

	DMA_PRIO_MEDIUM = 1,

	DMA_PRIO_LOW = 2

};

struct imx_dma_data {

	int dma_request; /* DMA request line */

	enum sdma_peripheral_type peripheral_type;

	int priority;

};

static inline int imx_dma_is_ipu(struct dma_chan *chan)

{

	return !strcmp(dev_name(chan->device->dev), "ipu-core");

}

static inline int imx_dma_is_general_purpose(struct dma_chan *chan)

{

	return !strcmp(dev_name(chan->device->dev), "imx-sdma") ||

		!strcmp(dev_name(chan->device->dev), "imx-dma");

}

#endif

#ifndef __MACH_MXC_SDMA_H__

#define __MACH_MXC_SDMA_H__

/**

 * struct sdma_platform_data - platform specific data for SDMA engine

 *

 * @sdma_version	The version of this SDMA engine

 * @cpu_name		used to generate the firmware name

 * @to_version		CPU Tape out version

 */

struct sdma_platform_data {

	int sdma_version;

	char *cpu_name;

	int to_version;

};

#endif /* __MACH_MXC_SDMA_H__ */

/*

 * Freescale MPC83XX / MPC85XX DMA Controller

 *

 * Copyright (c) 2009 Ira W. Snyder <iws@ovro.caltech.edu>

 *

 * This file is licensed under the terms of the GNU General Public License

 * version 2. This program is licensed "as is" without any warranty of any

 * kind, whether express or implied.

 */

#ifndef __ARCH_POWERPC_ASM_FSLDMA_H__

#define __ARCH_POWERPC_ASM_FSLDMA_H__

#include <linux/slab.h>

#include <linux/dmaengine.h>

/*

 * Definitions for the Freescale DMA controller's DMA_SLAVE implemention

 *

 * The Freescale DMA_SLAVE implementation was designed to handle many-to-many

 * transfers. An example usage would be an accelerated copy between two

 * scatterlists. Another example use would be an accelerated copy from

 * multiple non-contiguous device buffers into a single scatterlist.

 *

 * A DMA_SLAVE transaction is defined by a struct fsl_dma_slave. This

 * structure contains a list of hardware addresses that should be copied

 * to/from the scatterlist passed into device_prep_slave_sg(). The structure

 * also has some fields to enable hardware-specific features.

 */

/**

 * struct fsl_dma_hw_addr

 * @entry: linked list entry

 * @address: the hardware address

 * @length: length to transfer

 *

 * Holds a single physical hardware address / length pair for use

 * with the DMAEngine DMA_SLAVE API.

 */

struct fsl_dma_hw_addr {

	struct list_head entry;

	dma_addr_t address;

	size_t length;

};

/**

 * struct fsl_dma_slave

 * @addresses: a linked list of struct fsl_dma_hw_addr structures

 * @request_count: value for DMA request count

 * @src_loop_size: setup and enable constant source-address DMA transfers

 * @dst_loop_size: setup and enable constant destination address DMA transfers

 * @external_start: enable externally started DMA transfers

 * @external_pause: enable externally paused DMA transfers

 *

 * Holds a list of address / length pairs for use with the DMAEngine

 * DMA_SLAVE API implementation for the Freescale DMA controller.

 */

struct fsl_dma_slave {

	/* List of hardware address/length pairs */

	struct list_head addresses;

	/* Support for extra controller features */

	unsigned int request_count;

	unsigned int src_loop_size;

	unsigned int dst_loop_size;

	bool external_start;

	bool external_pause;

};

/**

 * fsl_dma_slave_append - add an address/length pair to a struct fsl_dma_slave

 * @slave: the &struct fsl_dma_slave to add to

 * @address: the hardware address to add

 * @length: the length of bytes to transfer from @address

 *

 * Add a hardware address/length pair to a struct fsl_dma_slave. Returns 0 on

 * success, -ERRNO otherwise.

 */

static inline int fsl_dma_slave_append(struct fsl_dma_slave *slave,

				       dma_addr_t address, size_t length)

{

	struct fsl_dma_hw_addr *addr;

	addr = kzalloc(sizeof(*addr), GFP_ATOMIC);

	if (!addr)

		return -ENOMEM;

	INIT_LIST_HEAD(&addr->entry);

	addr->address = address;

	addr->length = length;

	list_add_tail(&addr->entry, &slave->addresses);

	return 0;

}

/**

 * fsl_dma_slave_free - free a struct fsl_dma_slave

 * @slave: the struct fsl_dma_slave to free

 *

 * Free a struct fsl_dma_slave and all associated address/length pairs

 */

static inline void fsl_dma_slave_free(struct fsl_dma_slave *slave)

{

	struct fsl_dma_hw_addr *addr, *tmp;

	if (slave) {

		list_for_each_entry_safe(addr, tmp, &slave->addresses, entry) {

			list_del(&addr->entry);

			kfree(addr);

		}

		kfree(slave);

	}

}

/**

 * fsl_dma_slave_alloc - allocate a struct fsl_dma_slave

 * @gfp: the flags to pass to kmalloc when allocating this structure

 *

 * Allocate a struct fsl_dma_slave for use by the DMA_SLAVE API. Returns a new

 * struct fsl_dma_slave on success, or NULL on failure.

 */

static inline struct fsl_dma_slave *fsl_dma_slave_alloc(gfp_t gfp)

{

	struct fsl_dma_slave *slave;

	slave = kzalloc(sizeof(*slave), gfp);

	if (!slave)

		return NULL;

	INIT_LIST_HEAD(&slave->addresses);

	return slave;

}

#endif /* __ARCH_POWERPC_ASM_FSLDMA_H__ */

config ASYNC_TX_DISABLE_CHANNEL_SWITCH

	bool

config AMBA_PL08X

	bool "ARM PrimeCell PL080 or PL081 support"

	depends on ARM_AMBA && EXPERIMENTAL

	select DMA_ENGINE

	help

	  Platform has a PL08x DMAC device

	  which can provide DMA engine support

config INTEL_IOATDMA

	tristate "Intel I/OAT DMA support"

	depends on PCI && X86

	help

	  Enable support for the Topcliff PCH DMA engine.

config IMX_SDMA

	tristate "i.MX SDMA support"

	depends on ARCH_MX25 || ARCH_MX3 || ARCH_MX5

	select DMA_ENGINE

	help

	  Support the i.MX SDMA engine. This engine is integrated into

	  Freescale i.MX25/31/35/51 chips.

config IMX_DMA

	tristate "i.MX DMA support"

	depends on ARCH_MX1 || ARCH_MX21 || MACH_MX27

	select DMA_ENGINE

	help

	  Support the i.MX DMA engine. This engine is integrated into

	  Freescale i.MX1/21/27 chips.

config DMA_ENGINE

	bool