Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 635c6700 authored by Tony Truong's avatar Tony Truong
Browse files

ARM: dts: msm: add PCIe nodes for msm8994 



Add nodes for PCIe controllers to msm8994 device tree.

Change-Id: Ia828b7e177003bf3f98a56062ffe3e25b88883e6
Signed-off-by: default avatarTony Truong <truong@codeaurora.org>
parent ee888118

arch/arm/boot/dts/qcom/msm8994.dtsi

+139 −0
Original line number Diff line number Diff line
@@ -443,6 +443,145 @@ 
		clock-names = "dfab_clk", "dma_bam_pclk";

	};



	pcie0: qcom,pcie@fc520000 {

		compatible = "qcom,pci-msm";

		cell-index = <0>;



		reg = <0xfc520000 0x2000>,

		      <0xfc526000 0x1000>,

		      <0xff000000 0xf1d>,

		      <0xff000f20 0xa8>,

		      <0xff100000 0x1000>,

		      <0xff200000 0x100000>,

		      <0xff300000 0xd00000>;



		reg-names = "parf", "phy", "dm_core", "elbi",

				"conf", "io", "bars";



		#address-cells = <0>;

		interrupt-parent = <&pcie0>;

		interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0xffffffff>;

		interrupt-map = <0 &intc 0 243 0

				1 &intc 0 244 0

				2 &intc 0 245 0

				3 &intc 0 247 0

				4 &intc 0 248 0

				5 &intc 0 249 0

				6 &intc 0 250 0

				7 &intc 0 251 0

				8 &intc 0 252 0

				9 &intc 0 253 0

				10 &intc 0 254 0

				11 &intc 0 255 0>;



		interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d",

				"int_pls_pme", "int_pme_legacy", "int_pls_err",

				"int_aer_legacy", "int_pls_link_up",

				"int_pls_link_down", "int_bridge_flush_n";



		pinctrl-names = "default";

		pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;



		perst-gpio = <&msm_gpio 53 0>;

		wake-gpio = <&msm_gpio 55 0>;



		gdsc-vdd-supply = <&gdsc_pcie_0>;

		vreg-1.8-supply = <&pm8994_l12>;

		vreg-0.9-supply = <&pm8994_l28>;



		qcom,msi-gicm-addr = <0xf9006040>;

		qcom,msi-gicm-base = <0x180>;



		clocks = <&clock_gcc clk_gcc_pcie_0_pipe_clk>,

			<&clock_rpm clk_ln_bb_clk>,

			<&clock_gcc clk_gcc_pcie_0_aux_clk>,

			<&clock_gcc clk_gcc_pcie_0_cfg_ahb_clk>,

			<&clock_gcc clk_gcc_pcie_0_mstr_axi_clk>,

			<&clock_gcc clk_gcc_pcie_0_slv_axi_clk>,

			<&clock_gcc clk_pcie_0_phy_ldo>,

			<&clock_gcc clk_gcc_pcie_phy_0_reset>;



		clock-names =  "pcie_0_pipe_clk", "pcie_0_ref_clk_src", "pcie_0_aux_clk",

			"pcie_0_cfg_ahb_clk", "pcie_0_mstr_axi_clk",

			"pcie_0_slv_axi_clk", "pcie_0_ldo", "pcie_0_phy_reset";



		max-clock-frequency-hz = <125000000>, <0>, <1011000>, <0>, <0>, <0>, <0>, <0>;

	};



	pcie1: qcom,pcie@fc528000 {

		compatible = "qcom,pci-msm";

		cell-index = <1>;



		reg = <0xfc528000 0x2000>,

		    <0xfc52e000  0x1000>,

		    <0xf8800000 0xf1d>,

		    <0xf8800F20 0xa8>,

		    <0xf8900000 0x1000>,

		    <0xf8a00000 0x100000>,

		    <0xf8b00000 0x4fffff>;



		reg-names = "parf", "phy", "dm_core", "elbi",

				"conf", "io", "bars";



		#address-cells = <0>;

		interrupt-parent = <&pcie1>;

		interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0xffffffff>;

		interrupt-map = <0 &intc 0 271 0

				1 &intc 0 272 0

				2 &intc 0 273 0

				3 &intc 0 274 0

				4 &intc 0 275 0

				5 &intc 0 276 0

				6 &intc 0 277 0

				7 &intc 0 278 0

				8 &intc 0 279 0

				9 &intc 0 280 0

				10 &intc 0 281 0

				11 &intc 0 282 0>;



		interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d",

				"int_pls_pme", "int_pme_legacy", "int_pls_err",

				"int_aer_legacy", "int_pls_link_up",

				"int_pls_link_down", "int_bridge_flush_n";



		pinctrl-names = "default";

		pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;



		perst-gpio = <&msm_gpio 35 0>;

		wake-gpio = <&msm_gpio 37 0>;



		gdsc-vdd-supply = <&gdsc_pcie_1>;

		vreg-1.8-supply = <&pm8994_l12>;

		vreg-0.9-supply = <&pm8994_l28>;



		qcom,l1ss-supported;

		qcom,aux-clk-sync;



		qcom,msi-gicm-addr = <0xf9007040>;

		qcom,msi-gicm-base = <0x1a0>;



		qcom,ep-wakeirq;



		clocks = <&clock_gcc clk_gcc_pcie_1_pipe_clk>,

			<&clock_rpm clk_ln_bb_clk>,

			<&clock_gcc clk_gcc_pcie_1_aux_clk>,

			<&clock_gcc clk_gcc_pcie_1_cfg_ahb_clk>,

			<&clock_gcc clk_gcc_pcie_1_mstr_axi_clk>,

			<&clock_gcc clk_gcc_pcie_1_slv_axi_clk>,

			<&clock_gcc clk_pcie_1_phy_ldo>,

			<&clock_gcc clk_gcc_pcie_phy_1_reset>;



		clock-names =  "pcie_1_pipe_clk", "pcie_1_ref_clk_src", "pcie_1_aux_clk",

			"pcie_1_cfg_ahb_clk", "pcie_1_mstr_axi_clk",

			"pcie_1_slv_axi_clk", "pcie_1_ldo", "pcie_1_phy_reset";



		max-clock-frequency-hz = <125000000>, <0>, <1011000>, <0>, <0>, <0>, <0>, <0>;

	};



	ipa_hw: qcom,ipa@fd4c0000 {

		compatible = "qcom,ipa";

		reg = <0xfd4c0000 0x29000>,