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Commit 634cdca5 authored by John Fastabend's avatar John Fastabend Committed by Jeff Kirsher
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ixgbe: PFC not cleared on X540 devices



X540 devices do not clear PFC before sets. This results in
the device possibly responding to PFC frames that the user
has disabled. Although it would also be wrong for the peer
to be transmitting these frames. Now we clear the register
before set.

Signed-off-by: default avatarJohn Fastabend <john.r.fastabend@intel.com>
Tested-by: default avatarRoss Brattain <ross.b.brattain@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent e7589eab
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+3 −1
Original line number Original line Diff line number Diff line
@@ -252,8 +252,10 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en)
		reg &= ~IXGBE_MFLCN_RFCE;
		reg &= ~IXGBE_MFLCN_RFCE;
		reg |= IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_DPF;
		reg |= IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_DPF;


		if (hw->mac.type == ixgbe_mac_X540)
		if (hw->mac.type == ixgbe_mac_X540) {
			reg &= ~IXGBE_MFLCN_RPFCE_MASK;
			reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;
			reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;
		}


		IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
		IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);


+1 −0
Original line number Original line Diff line number Diff line
@@ -1834,6 +1834,7 @@ enum {
#define IXGBE_MFLCN_DPF         0x00000002 /* Discard Pause Frame */
#define IXGBE_MFLCN_DPF         0x00000002 /* Discard Pause Frame */
#define IXGBE_MFLCN_RPFCE       0x00000004 /* Receive Priority FC Enable */
#define IXGBE_MFLCN_RPFCE       0x00000004 /* Receive Priority FC Enable */
#define IXGBE_MFLCN_RFCE        0x00000008 /* Receive FC Enable */
#define IXGBE_MFLCN_RFCE        0x00000008 /* Receive FC Enable */
#define IXGBE_MFLCN_RPFCE_MASK	0x00000FE0 /* Receive FC Mask */


#define IXGBE_MFLCN_RPFCE_SHIFT		 4
#define IXGBE_MFLCN_RPFCE_SHIFT		 4