x86, VisWS: turn into generic arch, remove leftover files

mflags-$(CONFIG_X86_VOYAGER)	:= -Iinclude/asm-x86/mach-voyager

mflags-$(CONFIG_X86_VOYAGER)	:= -Iinclude/asm-x86/mach-voyager

mcore-$(CONFIG_X86_VOYAGER)	:= arch/x86/mach-voyager/

mcore-$(CONFIG_X86_VOYAGER)	:= arch/x86/mach-voyager/

# VISWS subarch support

#mflags-$(CONFIG_X86_VISWS)	:= -Iinclude/asm-x86/mach-visws

#mcore-$(CONFIG_X86_VISWS)	:= arch/x86/mach-visws/

# generic subarchitecture

# generic subarchitecture

mflags-$(CONFIG_X86_GENERICARCH):= -Iinclude/asm-x86/mach-generic

mflags-$(CONFIG_X86_GENERICARCH):= -Iinclude/asm-x86/mach-generic

fcore-$(CONFIG_X86_GENERICARCH)	+= arch/x86/mach-generic/

fcore-$(CONFIG_X86_GENERICARCH)	+= arch/x86/mach-generic/

#

# Makefile for the linux kernel.

#

obj-y				:= setup.o setup_visws.o traps.o

obj-$(CONFIG_X86_VISWS_APIC)	+= visws_apic.o

/*

 *	Machine specific setup for generic

 */

#include <linux/smp.h>

#include <linux/init.h>

#include <linux/interrupt.h>

#include <asm/acpi.h>

#include <asm/arch_hooks.h>

#include <asm/e820.h>

#include <asm/setup.h>

/*

 * Any quirks to be performed to initialize timers/irqs/etc?

 */

int (*arch_time_init_quirk)(void);

int (*arch_pre_intr_init_quirk)(void);

int (*arch_intr_init_quirk)(void);

int (*arch_trap_init_quirk)(void);

#ifdef CONFIG_HOTPLUG_CPU

#define DEFAULT_SEND_IPI	(1)

#else

#define DEFAULT_SEND_IPI	(0)

#endif

int no_broadcast=DEFAULT_SEND_IPI;

/**

 * pre_intr_init_hook - initialisation prior to setting up interrupt vectors

 *

 * Description:

 *	Perform any necessary interrupt initialisation prior to setting up

 *	the "ordinary" interrupt call gates.  For legacy reasons, the ISA

 *	interrupts should be initialised here if the machine emulates a PC

 *	in any way.

 **/

void __init pre_intr_init_hook(void)

{

	if (arch_pre_intr_init_quirk) {

		if (arch_pre_intr_init_quirk())

			return;

	}

	init_ISA_irqs();

}

/*

 * IRQ2 is cascade interrupt to second interrupt controller

 */

static struct irqaction irq2 = {

	.handler = no_action,

	.mask = CPU_MASK_NONE,

	.name = "cascade",

};

/**

 * intr_init_hook - post gate setup interrupt initialisation

 *

 * Description:

 *	Fill in any interrupts that may have been left out by the general

 *	init_IRQ() routine.  interrupts having to do with the machine rather

 *	than the devices on the I/O bus (like APIC interrupts in intel MP

 *	systems) are started here.

 **/

void __init intr_init_hook(void)

{

	if (arch_intr_init_quirk) {

		if (arch_intr_init_quirk())

			return;

	}

#ifdef CONFIG_X86_LOCAL_APIC

	apic_intr_init();

#endif

	if (!acpi_ioapic)

		setup_irq(2, &irq2);

}

/**

 * pre_setup_arch_hook - hook called prior to any setup_arch() execution

 *

 * Description:

 *	generally used to activate any machine specific identification

 *	routines that may be needed before setup_arch() runs.  On VISWS

 *	this is used to get the board revision and type.

 **/

void __init pre_setup_arch_hook(void)

{

}

/**

 * trap_init_hook - initialise system specific traps

 *

 * Description:

 *	Called as the final act of trap_init().  Used in VISWS to initialise

 *	the various board specific APIC traps.

 **/

void __init trap_init_hook(void)

{

	if (arch_trap_init_quirk) {

		if (arch_trap_init_quirk())

			return;

	}

}

static struct irqaction irq0  = {

	.handler = timer_interrupt,

	.flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_IRQPOLL,

	.mask = CPU_MASK_NONE,

	.name = "timer"

};

/**

 * time_init_hook - do any specific initialisations for the system timer.

 *

 * Description:

 *	Must plug the system timer interrupt source at HZ into the IRQ listed

 *	in irq_vectors.h:TIMER_IRQ

 **/

void __init time_init_hook(void)

{

	if (arch_time_init_quirk) {

		/*

		 * A nonzero return code does not mean failure, it means

		 * that the architecture quirk does not want any

		 * generic (timer) setup to be performed after this:

		 */

		if (arch_time_init_quirk())

			return;

	}

	irq0.mask = cpumask_of_cpu(0);

	setup_irq(0, &irq0);

}

#ifdef CONFIG_MCA

/**

 * mca_nmi_hook - hook into MCA specific NMI chain

 *

 * Description:

 *	The MCA (Microchannel Architecture) has an NMI chain for NMI sources

 *	along the MCA bus.  Use this to hook into that chain if you will need

 *	it.

 **/

void mca_nmi_hook(void)

{

	/* If I recall correctly, there's a whole bunch of other things that

	 * we can do to check for NMI problems, but that's all I know about

	 * at the moment.

	 */

	printk("NMI generated from unknown source!\n");

}

#endif

static __init int no_ipi_broadcast(char *str)

{

	get_option(&str, &no_broadcast);

	printk ("Using %s mode\n", no_broadcast ? "No IPI Broadcast" :

											"IPI Broadcast");

	return 1;

}

__setup("no_ipi_broadcast=", no_ipi_broadcast);

static int __init print_ipi_mode(void)

{

	printk ("Using IPI %s mode\n", no_broadcast ? "No-Shortcut" :

											"Shortcut");

	return 0;

}

late_initcall(print_ipi_mode);

/*

 *  Unmaintained SGI Visual Workstation support.

 *  Split out from setup.c by davej@suse.de

 */

#include <linux/interrupt.h>

#include <linux/module.h>

#include <linux/init.h>

#include <linux/smp.h>

#include <asm/visws/cobalt.h>

#include <asm/visws/piix4.h>

#include <asm/arch_hooks.h>

#include <asm/fixmap.h>

#include <asm/reboot.h>

#include <asm/setup.h>

#include <asm/e820.h>

#include <asm/smp.h>

#include <asm/io.h>

#include <mach_ipi.h>

#include "mach_apic.h"

#include <linux/init.h>

#include <linux/smp.h>

char visws_board_type	= -1;

char visws_board_rev	= -1;

int is_visws_box(void)

{

	return visws_board_type >= 0;

}

static int __init visws_time_init_quirk(void)

{

	printk(KERN_INFO "Starting Cobalt Timer system clock\n");

	/* Set the countdown value */

	co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ);

	/* Start the timer */

	co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) | CO_CTRL_TIMERUN);

	/* Enable (unmask) the timer interrupt */

	co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK);

	/*

	 * Zero return means the generic timer setup code will set up

	 * the standard vector:

	 */

	return 0;

}

static int __init visws_pre_intr_init_quirk(void)

{

	init_VISWS_APIC_irqs();

	/*

	 * We dont want ISA irqs to be set up by the generic code:

	 */

	return 1;

}

/* Quirk for machine specific memory setup. */

#define MB (1024 * 1024)

unsigned long sgivwfb_mem_phys;

unsigned long sgivwfb_mem_size;

EXPORT_SYMBOL(sgivwfb_mem_phys);

EXPORT_SYMBOL(sgivwfb_mem_size);

long long mem_size __initdata = 0;

static char * __init visws_memory_setup_quirk(void)

{

	long long gfx_mem_size = 8 * MB;

	mem_size = boot_params.alt_mem_k;

	if (!mem_size) {

		printk(KERN_WARNING "Bootloader didn't set memory size, upgrade it !\n");

		mem_size = 128 * MB;

	}

	/*

	 * this hardcodes the graphics memory to 8 MB

	 * it really should be sized dynamically (or at least

	 * set as a boot param)

	 */

	if (!sgivwfb_mem_size) {

		printk(KERN_WARNING "Defaulting to 8 MB framebuffer size\n");

		sgivwfb_mem_size = 8 * MB;

	}

	/*

	 * Trim to nearest MB

	 */

	sgivwfb_mem_size &= ~((1 << 20) - 1);

	sgivwfb_mem_phys = mem_size - gfx_mem_size;

	e820_add_region(0, LOWMEMSIZE(), E820_RAM);

	e820_add_region(HIGH_MEMORY, mem_size - sgivwfb_mem_size - HIGH_MEMORY, E820_RAM);

	e820_add_region(sgivwfb_mem_phys, sgivwfb_mem_size, E820_RESERVED);

	return "PROM";

}

static void visws_machine_emergency_restart(void)

{

	/*

	 * Visual Workstations restart after this

	 * register is poked on the PIIX4

	 */

	outb(PIIX4_RESET_VAL, PIIX4_RESET_PORT);

}

static void visws_machine_power_off(void)

{

	unsigned short pm_status;

/*	extern unsigned int pci_bus0; */

	while ((pm_status = inw(PMSTS_PORT)) & 0x100)

		outw(pm_status, PMSTS_PORT);

	outw(PM_SUSPEND_ENABLE, PMCNTRL_PORT);

	mdelay(10);

#define PCI_CONF1_ADDRESS(bus, devfn, reg) \

	(0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3))

/*	outl(PCI_CONF1_ADDRESS(pci_bus0, SPECIAL_DEV, SPECIAL_REG), 0xCF8); */

	outl(PIIX_SPECIAL_STOP, 0xCFC);

}

static int __init visws_get_smp_config_quirk(unsigned int early)

{

	/*

	 * Prevent MP-table parsing by the generic code:

	 */

	return 1;

}

extern unsigned int __cpuinitdata maxcpus;

/*

 * The Visual Workstation is Intel MP compliant in the hardware

 * sense, but it doesn't have a BIOS(-configuration table).

 * No problem for Linux.

 */

static void __init MP_processor_info (struct mpc_config_processor *m)

{

	int ver, logical_apicid;

	physid_mask_t apic_cpus;

	if (!(m->mpc_cpuflag & CPU_ENABLED))

		return;

	logical_apicid = m->mpc_apicid;

	printk(KERN_INFO "%sCPU #%d %u:%u APIC version %d\n",

	       m->mpc_cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "",

	       m->mpc_apicid,

	       (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,

	       (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,

	       m->mpc_apicver);

	if (m->mpc_cpuflag & CPU_BOOTPROCESSOR)

		boot_cpu_physical_apicid = m->mpc_apicid;

	ver = m->mpc_apicver;

	if ((ver >= 0x14 && m->mpc_apicid >= 0xff) || m->mpc_apicid >= 0xf) {

		printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",

			m->mpc_apicid, MAX_APICS);

		return;

	}

	apic_cpus = apicid_to_cpu_present(m->mpc_apicid);

	physids_or(phys_cpu_present_map, phys_cpu_present_map, apic_cpus);

	/*

	 * Validate version

	 */

	if (ver == 0x0) {

		printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! "

			"fixing up to 0x10. (tell your hw vendor)\n",

			m->mpc_apicid);

		ver = 0x10;

	}

	apic_version[m->mpc_apicid] = ver;

}

int __init visws_find_smp_config_quirk(unsigned int reserve)

{

	struct mpc_config_processor *mp = phys_to_virt(CO_CPU_TAB_PHYS);

	unsigned short ncpus = readw(phys_to_virt(CO_CPU_NUM_PHYS));

	if (ncpus > CO_CPU_MAX) {

		printk(KERN_WARNING "find_visws_smp: got cpu count of %d at %p\n",

			ncpus, mp);

		ncpus = CO_CPU_MAX;

	}

	if (ncpus > maxcpus)

		ncpus = maxcpus;

#ifdef CONFIG_X86_LOCAL_APIC

	smp_found_config = 1;

#endif

	while (ncpus--)

		MP_processor_info(mp++);

	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;

	return 1;

}

extern int visws_trap_init_quirk(void);

void __init visws_early_detect(void)

{

	int raw;

	visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG)

							 >> PIIX_GPI_BD_SHIFT;

	if (visws_board_type < 0)

		return;

	/*

	 * Install special quirks for timer, interrupt and memory setup:

	 */

	arch_time_init_quirk		= visws_time_init_quirk;

	arch_pre_intr_init_quirk	= visws_pre_intr_init_quirk;

	arch_memory_setup_quirk		= visws_memory_setup_quirk;

	/*

	 * Fall back to generic behavior for traps:

	 */

	arch_intr_init_quirk		= NULL;

	arch_trap_init_quirk		= visws_trap_init_quirk;

	/*

	 * Install reboot quirks:

	 */

	pm_power_off			= visws_machine_power_off;

	machine_ops.emergency_restart	= visws_machine_emergency_restart;

	/*

	 * Do not use broadcast IPIs:

	 */

	no_broadcast = 0;

	/*

	 * Override generic MP-table parsing:

	 */

	mach_get_smp_config_quirk	= visws_get_smp_config_quirk;

	mach_find_smp_config_quirk	= visws_find_smp_config_quirk;

	/*

	 * Get Board rev.

	 * First, we have to initialize the 307 part to allow us access

	 * to the GPIO registers.  Let's map them at 0x0fc0 which is right

	 * after the PIIX4 PM section.

	 */

	outb_p(SIO_DEV_SEL, SIO_INDEX);

	outb_p(SIO_GP_DEV, SIO_DATA);	/* Talk to GPIO regs. */

	outb_p(SIO_DEV_MSB, SIO_INDEX);

	outb_p(SIO_GP_MSB, SIO_DATA);	/* MSB of GPIO base address */

	outb_p(SIO_DEV_LSB, SIO_INDEX);

	outb_p(SIO_GP_LSB, SIO_DATA);	/* LSB of GPIO base address */

	outb_p(SIO_DEV_ENB, SIO_INDEX);

	outb_p(1, SIO_DATA);		/* Enable GPIO registers. */

	/*

	 * Now, we have to map the power management section to write

	 * a bit which enables access to the GPIO registers.

	 * What lunatic came up with this shit?

	 */

	outb_p(SIO_DEV_SEL, SIO_INDEX);

	outb_p(SIO_PM_DEV, SIO_DATA);	/* Talk to GPIO regs. */

	outb_p(SIO_DEV_MSB, SIO_INDEX);

	outb_p(SIO_PM_MSB, SIO_DATA);	/* MSB of PM base address */

	outb_p(SIO_DEV_LSB, SIO_INDEX);

	outb_p(SIO_PM_LSB, SIO_DATA);	/* LSB of PM base address */

	outb_p(SIO_DEV_ENB, SIO_INDEX);

	outb_p(1, SIO_DATA);		/* Enable PM registers. */

	/*

	 * Now, write the PM register which enables the GPIO registers.

	 */

	outb_p(SIO_PM_FER2, SIO_PM_INDEX);

	outb_p(SIO_PM_GP_EN, SIO_PM_DATA);

	/*

	 * Now, initialize the GPIO registers.

	 * We want them all to be inputs which is the

	 * power on default, so let's leave them alone.

	 * So, let's just read the board rev!

	 */

	raw = inb_p(SIO_GP_DATA1);

	raw &= 0x7f;	/* 7 bits of valid board revision ID. */

	if (visws_board_type == VISWS_320) {

		if (raw < 0x6) {

			visws_board_rev = 4;

		} else if (raw < 0xc) {

			visws_board_rev = 5;

		} else {

			visws_board_rev = 6;

		}

	} else if (visws_board_type == VISWS_540) {

			visws_board_rev = 2;

		} else {

			visws_board_rev = raw;

		}

	printk(KERN_INFO "Silicon Graphics Visual Workstation %s (rev %d) detected\n",

	       (visws_board_type == VISWS_320 ? "320" :

	       (visws_board_type == VISWS_540 ? "540" :

		"unknown")), visws_board_rev);

}

/* VISWS traps */

#include <linux/sched.h>

#include <linux/kernel.h>

#include <linux/init.h>

#include <linux/pci.h>

#include <linux/pci_ids.h>

#include <asm/io.h>

#include <asm/apic.h>

#include <asm/arch_hooks.h>

#include <asm/visws/cobalt.h>

#include <asm/visws/lithium.h>

#define A01234 (LI_INTA_0 | LI_INTA_1 | LI_INTA_2 | LI_INTA_3 | LI_INTA_4)

#define BCD (LI_INTB | LI_INTC | LI_INTD)

#define ALLDEVS (A01234 | BCD)

static __init void lithium_init(void)

{

	set_fixmap(FIX_LI_PCIA, LI_PCI_A_PHYS);

	set_fixmap(FIX_LI_PCIB, LI_PCI_B_PHYS);

	if ((li_pcia_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||

	    (li_pcia_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {

		printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'A');

/*		panic("This machine is not SGI Visual Workstation 320/540"); */

	}

	if ((li_pcib_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||

	    (li_pcib_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {

		printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'B');

/*		panic("This machine is not SGI Visual Workstation 320/540"); */

	}

	li_pcia_write16(LI_PCI_INTEN, ALLDEVS);

	li_pcib_write16(LI_PCI_INTEN, ALLDEVS);

}

static __init void cobalt_init(void)

{

	/*

	 * On normal SMP PC this is used only with SMP, but we have to

	 * use it and set it up here to start the Cobalt clock

	 */

	set_fixmap(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE);

	setup_local_APIC();

	printk(KERN_INFO "Local APIC Version %#x, ID %#x\n",

		(unsigned int)apic_read(APIC_LVR),

		(unsigned int)apic_read(APIC_ID));

	set_fixmap(FIX_CO_CPU, CO_CPU_PHYS);

	set_fixmap(FIX_CO_APIC, CO_APIC_PHYS);

	printk(KERN_INFO "Cobalt Revision %#lx, APIC ID %#lx\n",

		co_cpu_read(CO_CPU_REV), co_apic_read(CO_APIC_ID));

	/* Enable Cobalt APIC being careful to NOT change the ID! */

	co_apic_write(CO_APIC_ID, co_apic_read(CO_APIC_ID) | CO_APIC_ENABLE);

	printk(KERN_INFO "Cobalt APIC enabled: ID reg %#lx\n",

		co_apic_read(CO_APIC_ID));

}

int __init visws_trap_init_quirk(void)

{

	lithium_init();

	cobalt_init();

	return 1;

}