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Commit 62b48b39 authored by Laxminath Kasam's avatar Laxminath Kasam
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ASoC: msm8x16-wcd: make default spkr_ocp hold enable



Currently, OCP hold is set to zero by default which is
preventing the PA from holding the shutdown state.
Set this bit to enable OCP hold by default. Once hold is set
PA would shut down immediately during overcurrent and hold
that state unless SPKR_PA_EN bit is toggled.

Change-Id: Ib37edddea5a4a34f5f6d046d3bf3baa835598d89
Signed-off-by: default avatarLaxminath Kasam <lkasam@codeaurora.org>
parent 357078fe
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+2 −0
Original line number Diff line number Diff line
@@ -2981,6 +2981,7 @@ static const struct snd_soc_dapm_widget msm8x16_wcd_dapm_widgets[] = {
static const struct msm8x16_wcd_reg_mask_val msm8x16_wcd_reg_defaults[] = {
	MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x03),
	MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_CURRENT_LIMIT, 0x82),
	MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_OCP_CTL, 0xE1),
};

static const struct msm8x16_wcd_reg_mask_val msm8x16_wcd_reg_defaults_2_0[] = {
@@ -2994,6 +2995,7 @@ static const struct msm8x16_wcd_reg_mask_val msm8x16_wcd_reg_defaults_2_0[] = {
	MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL3, 0x0F),
	MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_CURRENT_LIMIT, 0x82),
	MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x03),
	MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_OCP_CTL, 0xE1),
};

static void msm8x16_wcd_update_reg_defaults(struct snd_soc_codec *codec)
+1 −1
Original line number Diff line number Diff line
@@ -264,7 +264,7 @@
#define MSM8X16_WCD_A_ANALOG_SPKR_ANA_BIAS_SET		(0x1B3)
#define MSM8X16_WCD_A_ANALOG_SPKR_ANA_BIAS_SET__POR		(0x4D)
#define MSM8X16_WCD_A_ANALOG_SPKR_OCP_CTL		(0x1B4)
#define MSM8X16_WCD_A_ANALOG_SPKR_OCP_CTL__POR			(0xA1)
#define MSM8X16_WCD_A_ANALOG_SPKR_OCP_CTL__POR			(0xE1)
#define MSM8X16_WCD_A_ANALOG_SPKR_PWRSTG_CTL		(0x1B5)
#define MSM8X16_WCD_A_ANALOG_SPKR_PWRSTG_CTL__POR		(0x1E)
#define MSM8X16_WCD_A_ANALOG_SPKR_DRV_MISC		(0x1B6)