Loading arch/arm64/include/asm/io.h +2 −0 Original line number Diff line number Diff line Loading @@ -142,6 +142,8 @@ static inline u64 __raw_readq_no_log(const volatile void __iomem *addr) #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c))) #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c))) #define readl_relaxed_no_log(c) ({ u32 __v = le32_to_cpu((__force __le32)__raw_readl_no_log(c)); __v; }) #define writel_relaxed_no_log(v,c) ((void)__raw_writel_no_log((__force u32)cpu_to_le32(v),(c))) /* * I/O memory access primitives. Reads are ordered relative to any * following Normal memory access. Writes are ordered relative to any prior Loading Loading
arch/arm64/include/asm/io.h +2 −0 Original line number Diff line number Diff line Loading @@ -142,6 +142,8 @@ static inline u64 __raw_readq_no_log(const volatile void __iomem *addr) #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c))) #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c))) #define readl_relaxed_no_log(c) ({ u32 __v = le32_to_cpu((__force __le32)__raw_readl_no_log(c)); __v; }) #define writel_relaxed_no_log(v,c) ((void)__raw_writel_no_log((__force u32)cpu_to_le32(v),(c))) /* * I/O memory access primitives. Reads are ordered relative to any * following Normal memory access. Writes are ordered relative to any prior Loading
