Merge branch 'drm-next-3.10-2' of git://people.freedesktop.org/~agd5f/linux into drm-next (61109488) · Commits · e / devices / android_kernel_sony_msm8994

drivers/gpu/drm/radeon/atom.c

+3 −3

Original line number	Original line	Diff line number	Diff line
	@@ -1394,10 +1394,10 @@ int atom_allocate_fb_scratch(struct atom_context *ctx)
	firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);		firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);

	DRM_DEBUG("atom firmware requested %08x %dkb\n",		DRM_DEBUG("atom firmware requested %08x %dkb\n",
	firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware,		le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),
	firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb);		le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb));

	usage_bytes = firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb * 1024;		usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024;
	}		}
	ctx->scratch_size_bytes = 0;		ctx->scratch_size_bytes = 0;
	if (usage_bytes == 0)		if (usage_bytes == 0)

drivers/gpu/drm/radeon/evergreen.c

+11 −92

Original line number	Original line	Diff line number	Diff line
	@@ -989,62 +989,10 @@ done:
	return r;		return r;
	}		}

	static int evergreen_uvd_calc_post_div(unsigned target_freq,
	unsigned vco_freq,
	unsigned *div)
	{
	/* target larger than vco frequency ? */
	if (vco_freq < target_freq)
	return -1; /* forget it */

	/* Fclk = Fvco / PDIV */
	*div = vco_freq / target_freq;

	/* we alway need a frequency less than or equal the target */
	if ((vco_freq / *div) > target_freq)
	*div += 1;

	/* dividers above 5 must be even */
	if (div > 5 && div % 2)
	*div += 1;

	/* out of range ? */
	if (*div >= 128)
	return -1; /* forget it */

	return vco_freq / *div;
	}

	static int evergreen_uvd_send_upll_ctlreq(struct radeon_device *rdev)
	{
	unsigned i;

	/* assert UPLL_CTLREQ */
	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);

	/* wait for CTLACK and CTLACK2 to get asserted */
	for (i = 0; i < 100; ++i) {
	uint32_t mask = UPLL_CTLACK_MASK \| UPLL_CTLACK2_MASK;
	if ((RREG32(CG_UPLL_FUNC_CNTL) & mask) == mask)
	break;
	mdelay(10);
	}
	if (i == 100)
	return -ETIMEDOUT;

	/* deassert UPLL_CTLREQ */
	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);

	return 0;
	}

	int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)		int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
	{		{
	/* start off with something large */		/* start off with something large */
	int optimal_diff_score = 0x7FFFFFF;		unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
	unsigned optimal_fb_div = 0, optimal_vclk_div = 0;
	unsigned optimal_dclk_div = 0, optimal_vco_freq = 0;
	unsigned vco_freq;
	int r;		int r;

	/* bypass vclk and dclk with bclk */		/* bypass vclk and dclk with bclk */
	@@ -1061,40 +1009,11 @@ int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
	return 0;		return 0;
	}		}

	/* loop through vco from low to high */		r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000,
	for (vco_freq = 125000; vco_freq <= 250000; vco_freq += 100) {		16384, 0x03FFFFFF, 0, 128, 5,
	unsigned fb_div = vco_freq / rdev->clock.spll.reference_freq * 16384;		&fb_div, &vclk_div, &dclk_div);
	int calc_clk, diff_score, diff_vclk, diff_dclk;		if (r)
	unsigned vclk_div, dclk_div;		return r;

	/* fb div out of range ? */
	if (fb_div > 0x03FFFFFF)
	break; /* it can oly get worse */

	/* calc vclk with current vco freq. */
	calc_clk = evergreen_uvd_calc_post_div(vclk, vco_freq, &vclk_div);
	if (calc_clk == -1)
	break; /* vco is too big, it has to stop. */
	diff_vclk = vclk - calc_clk;

	/* calc dclk with current vco freq. */
	calc_clk = evergreen_uvd_calc_post_div(dclk, vco_freq, &dclk_div);
	if (calc_clk == -1)
	break; /* vco is too big, it has to stop. */
	diff_dclk = dclk - calc_clk;

	/* determine if this vco setting is better than current optimal settings */
	diff_score = abs(diff_vclk) + abs(diff_dclk);
	if (diff_score < optimal_diff_score) {
	optimal_fb_div = fb_div;
	optimal_vclk_div = vclk_div;
	optimal_dclk_div = dclk_div;
	optimal_vco_freq = vco_freq;
	optimal_diff_score = diff_score;
	if (optimal_diff_score == 0)
	break; /* it can't get better than this */
	}
	}

	/* set VCO_MODE to 1 */		/* set VCO_MODE to 1 */
	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);		WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
	@@ -1108,7 +1027,7 @@ int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)

	mdelay(1);		mdelay(1);

	r = evergreen_uvd_send_upll_ctlreq(rdev);		r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
	if (r)		if (r)
	return r;		return r;

	@@ -1119,19 +1038,19 @@ int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
	WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);		WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);

	/* set feedback divider */		/* set feedback divider */
	WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(optimal_fb_div), ~UPLL_FB_DIV_MASK);		WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);

	/* set ref divider to 0 */		/* set ref divider to 0 */
	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);		WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);

	if (optimal_vco_freq < 187500)		if (fb_div < 307200)
	WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);		WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
	else		else
	WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);		WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);

	/* set PDIV_A and PDIV_B */		/* set PDIV_A and PDIV_B */
	WREG32_P(CG_UPLL_FUNC_CNTL_2,		WREG32_P(CG_UPLL_FUNC_CNTL_2,
	UPLL_PDIV_A(optimal_vclk_div) \| UPLL_PDIV_B(optimal_dclk_div),		UPLL_PDIV_A(vclk_div) \| UPLL_PDIV_B(dclk_div),
	~(UPLL_PDIV_A_MASK \| UPLL_PDIV_B_MASK));		~(UPLL_PDIV_A_MASK \| UPLL_PDIV_B_MASK));

	/* give the PLL some time to settle */		/* give the PLL some time to settle */
	@@ -1145,7 +1064,7 @@ int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
	/* switch from bypass mode to normal mode */		/* switch from bypass mode to normal mode */
	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);		WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);

	r = evergreen_uvd_send_upll_ctlreq(rdev);		r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
	if (r)		if (r)
	return r;		return r;

drivers/gpu/drm/radeon/evergreend.h

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -59,7 +59,7 @@
	# define UPLL_SLEEP_MASK 0x00000002		# define UPLL_SLEEP_MASK 0x00000002
	# define UPLL_BYPASS_EN_MASK 0x00000004		# define UPLL_BYPASS_EN_MASK 0x00000004
	# define UPLL_CTLREQ_MASK 0x00000008		# define UPLL_CTLREQ_MASK 0x00000008
	# define UPLL_REF_DIV_MASK 0x001F0000		# define UPLL_REF_DIV_MASK 0x003F0000
	# define UPLL_VCO_MODE_MASK 0x00000200		# define UPLL_VCO_MODE_MASK 0x00000200
	# define UPLL_CTLACK_MASK 0x40000000		# define UPLL_CTLACK_MASK 0x40000000
	# define UPLL_CTLACK2_MASK 0x80000000		# define UPLL_CTLACK2_MASK 0x80000000

drivers/gpu/drm/radeon/ni.c

+4 −2

drivers/gpu/drm/radeon/r600d.h

+4 −0

Original line number	Original line	Diff line number	Diff line
	@@ -1208,6 +1208,10 @@

	#define UVD_CONTEXT_ID 0xf6f4		#define UVD_CONTEXT_ID 0xf6f4

			# define UPLL_CTLREQ_MASK 0x00000008
			# define UPLL_CTLACK_MASK 0x40000000
			# define UPLL_CTLACK2_MASK 0x80000000

	/*		/*
	* PM4		* PM4
	*/		*/

Original line number	Original line	Diff line number	Diff line
	@@ -749,7 +749,8 @@ static void cayman_gpu_init(struct radeon_device *rdev)
	(rdev->pdev->device == 0x990F) \|\|		(rdev->pdev->device == 0x990F) \|\|
	(rdev->pdev->device == 0x9910) \|\|		(rdev->pdev->device == 0x9910) \|\|
	(rdev->pdev->device == 0x9917) \|\|		(rdev->pdev->device == 0x9917) \|\|
	(rdev->pdev->device == 0x9999)) {		(rdev->pdev->device == 0x9999) \|\|
			(rdev->pdev->device == 0x999C)) {
	rdev->config.cayman.max_simds_per_se = 6;		rdev->config.cayman.max_simds_per_se = 6;
	rdev->config.cayman.max_backends_per_se = 2;		rdev->config.cayman.max_backends_per_se = 2;
	} else if ((rdev->pdev->device == 0x9903) \|\|		} else if ((rdev->pdev->device == 0x9903) \|\|
	@@ -758,7 +759,8 @@ static void cayman_gpu_init(struct radeon_device *rdev)
	(rdev->pdev->device == 0x990D) \|\|		(rdev->pdev->device == 0x990D) \|\|
	(rdev->pdev->device == 0x990E) \|\|		(rdev->pdev->device == 0x990E) \|\|
	(rdev->pdev->device == 0x9913) \|\|		(rdev->pdev->device == 0x9913) \|\|
	(rdev->pdev->device == 0x9918)) {		(rdev->pdev->device == 0x9918) \|\|
			(rdev->pdev->device == 0x999D)) {
	rdev->config.cayman.max_simds_per_se = 4;		rdev->config.cayman.max_simds_per_se = 4;
	rdev->config.cayman.max_backends_per_se = 2;		rdev->config.cayman.max_backends_per_se = 2;
	} else if ((rdev->pdev->device == 0x9919) \|\|		} else if ((rdev->pdev->device == 0x9919) \|\|