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Commit 603cae11 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: mdss: update MDSS driver to support latency ram"

parents f7025d39 01c2186a
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+6 −5
Original line number Diff line number Diff line
@@ -90,11 +90,6 @@ Required properties
				offset within status register. Number of tuples
				defined should match the number of offsets
				defined in property: qcom,mdss-pipe-dma-off
- qcom,mdss-smp-data:		Array of shared memory pool data. There should
				be only two values in this property. The first
				value corresponds to the number of smp blocks
				and the second is the size of each block
				present in the mdss hardware.
- qcom,mdss-ctl-off:		Array of offset addresses for the available ctl
				hw blocks within MDP, these offsets are
				calculated from register "mdp_phys" defined in
@@ -238,6 +233,12 @@ Optional properties:
			settings used to setup MDSS QoS for best performance.
			The key used should be offset from "mdp_phys" register
			defined in reg property.
- qcom,mdss-smp-data:	Array of shared memory pool data for dynamic SMP. There
			should be only two values in this property. The first
			value corresponds to the number of smp blocks and the
			second is the size of each block present in the mdss
			hardware. This property is optional for MDP hardware
			with fix pixel latency ram.
- qcom,mdss-rot-block-size:	The size of a memory block (in pixels) to be used
				by the rotator. If this property is not specified,
				then a default value of 128 pixels would be used.
+1 −0
Original line number Diff line number Diff line
@@ -139,6 +139,7 @@ struct mdss_data_type {
	bool has_src_split;
	bool idle_pc_enabled;
	bool has_dst_split;
	bool has_pixel_ram;

	u32 rotator_ot_limit;
	u32 mdp_irq_mask;
+43 −25
Original line number Diff line number Diff line
@@ -1812,6 +1812,9 @@ static int mdss_mdp_parse_dt_pipe(struct platform_device *pdev)

	struct mdss_data_type *mdata = platform_get_drvdata(pdev);

	mdata->has_pixel_ram = !mdss_mdp_parse_dt_prop_len(pdev,
						"qcom,mdss-smp-data");

	mdata->nvig_pipes = mdss_mdp_parse_dt_prop_len(pdev,
				"qcom,mdss-pipe-vig-off");
	mdata->nrgb_pipes = mdss_mdp_parse_dt_prop_len(pdev,
@@ -1821,6 +1824,7 @@ static int mdss_mdp_parse_dt_pipe(struct platform_device *pdev)

	npipes = mdata->nvig_pipes + mdata->nrgb_pipes + mdata->ndma_pipes;

	if (!mdata->has_pixel_ram) {
		nfids  += mdss_mdp_parse_dt_prop_len(pdev,
				"qcom,mdss-pipe-vig-fetch-id");
		nfids  += mdss_mdp_parse_dt_prop_len(pdev,
@@ -1831,6 +1835,7 @@ static int mdss_mdp_parse_dt_pipe(struct platform_device *pdev)
			pr_err("device tree err: unequal number of pipes and smp ids");
			return -EINVAL;
		}
	}

	nxids += mdss_mdp_parse_dt_prop_len(pdev, "qcom,mdss-pipe-vig-xin-id");
	nxids += mdss_mdp_parse_dt_prop_len(pdev, "qcom,mdss-pipe-rgb-xin-id");
@@ -1846,7 +1851,7 @@ static int mdss_mdp_parse_dt_pipe(struct platform_device *pdev)
		return -ENOMEM;
	}

	ftch_id = kzalloc(sizeof(u32) * nfids, GFP_KERNEL);
	ftch_id = kzalloc(sizeof(u32) * npipes, GFP_KERNEL);
	if (!ftch_id) {
		pr_err("no mem assigned for ftch_id: kzalloc fail\n");
		rc = -ENOMEM;
@@ -1887,10 +1892,13 @@ static int mdss_mdp_parse_dt_pipe(struct platform_device *pdev)
		}
	}

	rc = mdss_mdp_parse_dt_handler(pdev, "qcom,mdss-pipe-vig-fetch-id",
		ftch_id, mdata->nvig_pipes);
	if (nfids) {
		rc = mdss_mdp_parse_dt_handler(pdev,
			"qcom,mdss-pipe-vig-fetch-id", ftch_id,
			mdata->nvig_pipes);
		if (rc)
			goto parse_fail;
	}

	rc = mdss_mdp_parse_dt_handler(pdev, "qcom,mdss-pipe-vig-xin-id",
		xin_id, mdata->nvig_pipes);
@@ -1910,10 +1918,13 @@ static int mdss_mdp_parse_dt_pipe(struct platform_device *pdev)

	setup_cnt += len;

	rc = mdss_mdp_parse_dt_handler(pdev, "qcom,mdss-pipe-rgb-fetch-id",
	if (nfids) {
		rc = mdss_mdp_parse_dt_handler(pdev,
			"qcom,mdss-pipe-rgb-fetch-id",
			ftch_id + mdata->nvig_pipes, mdata->nrgb_pipes);
		if (rc)
			goto parse_fail;
	}

	rc = mdss_mdp_parse_dt_handler(pdev, "qcom,mdss-pipe-rgb-xin-id",
		xin_id + mdata->nvig_pipes, mdata->nrgb_pipes);
@@ -1938,11 +1949,13 @@ static int mdss_mdp_parse_dt_pipe(struct platform_device *pdev)
	if (mdata->ndma_pipes) {
		dma_off = mdata->nvig_pipes + mdata->nrgb_pipes;

		if (nfids) {
			rc = mdss_mdp_parse_dt_handler(pdev,
				"qcom,mdss-pipe-dma-fetch-id",
				ftch_id + dma_off, mdata->ndma_pipes);
			if (rc)
				goto parse_fail;
		}

		rc = mdss_mdp_parse_dt_handler(pdev,
			"qcom,mdss-pipe-dma-xin-id",
@@ -2300,8 +2313,13 @@ static int mdss_mdp_parse_dt_smp(struct platform_device *pdev)
	const u32 *arr;

	num = mdss_mdp_parse_dt_prop_len(pdev, "qcom,mdss-smp-data");

	if (num != 2)
	/*
	 * This property is optional for targets with fix pixel ram. Rest
	 * must provide no. of smp and size of each block.
	 */
	if (!num)
		return 0;
	else if (num != 2)
		return -EINVAL;

	rc = mdss_mdp_parse_dt_handler(pdev, "qcom,mdss-smp-data", data, num);
+7 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@
#define MDSS_MDP_CURSOR_WIDTH 64
#define MDSS_MDP_CURSOR_HEIGHT 64
#define MDSS_MDP_CURSOR_SIZE (MDSS_MDP_CURSOR_WIDTH*MDSS_MDP_CURSOR_WIDTH*4)
#define MDSS_MDP_PIXEL_RAM_SIZE (50 * 1024)

#define MDP_CLK_DEFAULT_RATE	200000000
#define PHASE_STEP_SHIFT	21
@@ -616,6 +617,12 @@ static inline int mdss_mdp_get_wb_ctl_support(struct mdss_data_type *mdata,
				(mdata->nctl - mdata->nwb);
}

static inline int mdss_mdp_get_pixel_ram_size(struct mdss_data_type *mdata)
{
	return (mdata->mdp_rev == MDSS_MDP_HW_REV_107) ?
						MDSS_MDP_PIXEL_RAM_SIZE : 0;
}

irqreturn_t mdss_mdp_isr(int irq, void *ptr);
int mdss_iommu_attach(struct mdss_data_type *mdata);
int mdss_iommu_dettach(struct mdss_data_type *mdata);
+4 −2
Original line number Diff line number Diff line
@@ -2651,8 +2651,10 @@ static int mdss_fb_get_hw_caps(struct msm_fb_data_type *mfd,
	if (mdata->has_decimation)
		caps->features |= MDP_DECIMATION_EN;

	caps->max_smp_cnt = mdss_res->smp_mb_cnt;
	if (mdata->smp_mb_cnt) {
		caps->max_smp_cnt = mdata->smp_mb_cnt;
		caps->smp_per_pipe = mdata->smp_mb_per_pipe;
	}

	return 0;
}
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