Commit 5f66e4f6 authored Nov 19, 2014 by Anil Kumar Mamidala

ARM: dts: msm: Add property to not flush L1/L2 during power collapse



On 8909, the L1/L2 caches are flushed and invalidated by TZ. Add DT flag to
prevent flushing of L1/L2 cache during power collapse

Change-Id: I2c02b0d18e731dff930e6eb7bd330a6789573df9
Signed-off-by: Anil Kumar Mamidala <amami@codeaurora.org>

parent 1509a38c

arch/arm/boot/dts/qcom/msm8909-pm8909-pm.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -318,6 +318,7 @@
		qcom,pc-mode = "tz_l2_int";
		qcom,use-sync-timer;
		qcom,synced-clocks;
		qcom,tz-flushes-cache;
		};

		qcom,cpu-sleep-status@b088008{