Loading drivers/gpu/msm/a4xx_reg.h +2 −0 Original line number Diff line number Diff line Loading @@ -201,6 +201,8 @@ enum a4xx_rb_perfctr_rb_sel { #define A4XX_RBBM_CFG_DEBBUS_LOADIVT 0x95 #define A4XX_RBBM_POWER_CNTL_IP 0x98 #define A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0 0x99 #define A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 0x9a #define A4XX_RBBM_PERFCTR_CP_0_LO 0x9c #define A4XX_RBBM_PERFCTR_CP_0_HI 0x9d #define A4XX_RBBM_PERFCTR_CP_1_LO 0x9e Loading drivers/gpu/msm/adreno_a4xx.c +8 −0 Original line number Diff line number Diff line Loading @@ -546,6 +546,14 @@ static void a4xx_start(struct adreno_device *adreno_dev) kgsl_regwrite(device, A4XX_CP_DEBUG, A4XX_CP_DEBUG_DEFAULT | (adreno_is_a420(adreno_dev) ? (1 << 29) : 0)); /* On A430 enable SP regfile sleep for power savings */ if (!adreno_is_a420(adreno_dev)) { kgsl_regwrite(device, A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0, 0x00000441); kgsl_regwrite(device, A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1, 0x00000441); } a4xx_enable_hwcg(device); a4xx_enable_pc(adreno_dev); /* Loading Loading
drivers/gpu/msm/a4xx_reg.h +2 −0 Original line number Diff line number Diff line Loading @@ -201,6 +201,8 @@ enum a4xx_rb_perfctr_rb_sel { #define A4XX_RBBM_CFG_DEBBUS_LOADIVT 0x95 #define A4XX_RBBM_POWER_CNTL_IP 0x98 #define A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0 0x99 #define A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 0x9a #define A4XX_RBBM_PERFCTR_CP_0_LO 0x9c #define A4XX_RBBM_PERFCTR_CP_0_HI 0x9d #define A4XX_RBBM_PERFCTR_CP_1_LO 0x9e Loading
drivers/gpu/msm/adreno_a4xx.c +8 −0 Original line number Diff line number Diff line Loading @@ -546,6 +546,14 @@ static void a4xx_start(struct adreno_device *adreno_dev) kgsl_regwrite(device, A4XX_CP_DEBUG, A4XX_CP_DEBUG_DEFAULT | (adreno_is_a420(adreno_dev) ? (1 << 29) : 0)); /* On A430 enable SP regfile sleep for power savings */ if (!adreno_is_a420(adreno_dev)) { kgsl_regwrite(device, A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0, 0x00000441); kgsl_regwrite(device, A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1, 0x00000441); } a4xx_enable_hwcg(device); a4xx_enable_pc(adreno_dev); /* Loading