Merge "msm: camera: isp: Use epoch irq for SOF event" (5df890cc) · Commits · e / devices / android_kernel_sony_msm8994

drivers/media/platform/msm/camera_v2/isp/msm_isp.h

+12 −5

Original line number	Diff line number	Diff line
		@@ -96,6 +96,9 @@ struct msm_vfe_irq_ops {
		void (process_reg_update) (struct vfe_device vfe_dev,
		uint32_t irq_status0, uint32_t irq_status1,
		struct msm_isp_timestamp *ts);
		void (process_epoch_irq)(struct vfe_device vfe_dev,
		uint32_t irq_status0, uint32_t irq_status1,
		struct msm_isp_timestamp *ts);
		void (process_reset_irq) (struct vfe_device vfe_dev,
		uint32_t irq_status0, uint32_t irq_status1);
		void (process_halt_irq) (struct vfe_device vfe_dev,
		@@ -120,7 +123,8 @@ struct msm_vfe_axi_ops {
		enum msm_vfe_axi_stream_src stream_src,
		uint32_t io_format);
		void (cfg_framedrop) (struct vfe_device vfe_dev,
		struct msm_vfe_axi_stream *stream_info);
		struct msm_vfe_axi_stream *stream_info,
		uint32_t framedrop_pattern, uint32_t framedrop_period);
		void (clear_framedrop) (struct vfe_device vfe_dev,
		struct msm_vfe_axi_stream *stream_info);
		void (cfg_comp_mask) (struct vfe_device vfe_dev,
		@@ -160,7 +164,8 @@ struct msm_vfe_axi_ops {
		};

		struct msm_vfe_core_ops {
		void (reg_update) (struct vfe_device vfe_dev);
		void (reg_update)(struct vfe_device vfe_dev,
		enum msm_vfe_input_src frame_src);
		long (reset_hw) (struct vfe_device vfe_dev, uint32_t first_start,
		uint32_t blocking_call);
		int (init_hw) (struct vfe_device vfe_dev);
		@@ -192,7 +197,8 @@ struct msm_vfe_stats_ops {
		int (*get_stats_idx) (enum msm_isp_stats_type stats_type);
		int (check_streams) (struct msm_vfe_stats_stream stream_info);
		void (cfg_framedrop) (struct vfe_device vfe_dev,
		struct msm_vfe_stats_stream *stream_info);
		struct msm_vfe_stats_stream *stream_info,
		uint32_t framedrop_pattern, uint32_t framedrop_period);
		void (clear_framedrop) (struct vfe_device vfe_dev,
		struct msm_vfe_stats_stream *stream_info);
		void (cfg_comp_mask) (struct vfe_device vfe_dev,
		@@ -382,6 +388,7 @@ struct msm_vfe_axi_shared_data {
		uint32_t free_wm[MAX_NUM_WM];
		uint32_t wm_image_size[MAX_NUM_WM];
		enum msm_wm_ub_cfg_type wm_ub_cfg_policy;
		uint8_t reg_update_requested;
		uint8_t num_used_wm;
		uint8_t num_active_stream;
		uint8_t num_rdi_stream;
		@@ -390,8 +397,8 @@ struct msm_vfe_axi_shared_data {
		struct msm_vfe_axi_composite_info
		composite_info[MAX_NUM_COMPOSITE_MASK];
		uint8_t num_used_composite_mask;
		uint32_t stream_update;
		atomic_t axi_cfg_update;
		uint32_t stream_update[VFE_SRC_MAX];
		atomic_t axi_cfg_update[VFE_SRC_MAX];
		enum msm_isp_camif_update_state pipeline_update;
		struct msm_vfe_src_info src_info[VFE_SRC_MAX];
		uint16_t stream_handle_cnt;

drivers/media/platform/msm/camera_v2/isp/msm_isp32.c

+41 −52

Original line number	Diff line number	Diff line
		@@ -402,11 +402,10 @@ static void msm_vfe32_process_camif_irq(struct vfe_device *vfe_dev,
		if (vfe_dev->axi_data.src_info[VFE_PIX_0].raw_stream_count > 0
		&& vfe_dev->axi_data.src_info[VFE_PIX_0].
		pix_stream_count == 0) {
		msm_isp_sof_notify(vfe_dev, VFE_PIX_0, ts);
		if (vfe_dev->axi_data.stream_update)
		msm_isp_axi_stream_update(vfe_dev,
		(1 << VFE_PIX_0));
		msm_isp_update_framedrop_reg(vfe_dev, (1 << VFE_PIX_0));
		msm_isp_notify(vfe_dev, ISP_EVENT_SOF, VFE_PIX_0, ts);
		if (vfe_dev->axi_data.stream_update[VFE_PIX_0])
		msm_isp_axi_stream_update(vfe_dev, VFE_PIX_0);
		msm_isp_update_framedrop_reg(vfe_dev, VFE_PIX_0);
		}
		}
		}
		@@ -580,53 +579,54 @@ static void msm_vfe32_process_reg_update(struct vfe_device *vfe_dev,
		struct msm_isp_timestamp *ts)
		{
		uint32_t rdi_status;
		uint8_t input_src = 0x0;
		enum msm_vfe_input_src i;

		if (!(irq_status0 & 0x20) && !(irq_status1 & 0x1C000000))
		return;

		if (irq_status0 & BIT(5)) {
		msm_isp_sof_notify(vfe_dev, VFE_PIX_0, ts);
		input_src \|= (1 << VFE_PIX_0);
		}
		if (irq_status1 & BIT(26)) {
		msm_isp_sof_notify(vfe_dev, VFE_RAW_0, ts);
		input_src \|= (1 << VFE_RAW_0);
		}
		if (irq_status1 & BIT(27)) {
		msm_isp_sof_notify(vfe_dev, VFE_RAW_1, ts);
		input_src \|= (1 << VFE_RAW_1);
		}
		if (irq_status1 & BIT(28)) {
		msm_isp_sof_notify(vfe_dev, VFE_RAW_2, ts);
		input_src \|= (1 << VFE_RAW_2);
		}

		if (vfe_dev->axi_data.stream_update) {
		msm_isp_notify(vfe_dev, ISP_EVENT_SOF, VFE_PIX_0, ts);
		vfe_dev->hw_info->vfe_ops.core_ops.reg_update(vfe_dev,
		VFE_PIX_0);
		if (vfe_dev->axi_data.stream_update[VFE_PIX_0]) {
		rdi_status = msm_camera_io_r(vfe_dev->vfe_base +
		VFE32_XBAR_BASE(0));
		rdi_status \|= msm_camera_io_r(vfe_dev->vfe_base +
		VFE32_XBAR_BASE(4));

		if (((rdi_status & BIT(7)) \|\| (rdi_status & BIT(7)) \|\|
		(rdi_status & BIT(7)) \|\| (rdi_status & BIT(7))) &&
		(!(irq_status0 & 0x20)))
		if ((rdi_status & BIT(7)) && (!(irq_status0 & 0x20)))
		return;
		}

		if (vfe_dev->axi_data.stream_update)
		msm_isp_axi_stream_update(vfe_dev, input_src);
		if (atomic_read(&vfe_dev->stats_data.stats_update))
		msm_isp_stats_stream_update(vfe_dev);
		msm_isp_update_framedrop_reg(vfe_dev, input_src);
		}

		for (i = VFE_RAW_0; i <= VFE_RAW_2; i++) {
		if (irq_status1 & BIT(26 + (i - VFE_RAW_0))) {
		msm_isp_notify(vfe_dev, ISP_EVENT_SOF, i, ts);
		if (vfe_dev->axi_data.stream_update[i])
		msm_isp_axi_stream_update(vfe_dev, i);
		msm_isp_update_framedrop_reg(vfe_dev, i);

		vfe_dev->hw_info->vfe_ops.core_ops.reg_update(vfe_dev,
		i);
		}
		}

		msm_isp_update_error_frame_count(vfe_dev);

		vfe_dev->hw_info->vfe_ops.core_ops.
		reg_update(vfe_dev);
		return;
		}

		static void msm_vfe32_reg_update(
		struct vfe_device *vfe_dev)
		static void msm_vfe32_process_epoch_irq(struct vfe_device *vfe_dev,
		uint32_t irq_status0, uint32_t irq_status1,
		struct msm_isp_timestamp *ts)
		{
		/* Not supported */
		}

		static void msm_vfe32_reg_update(struct vfe_device *vfe_dev,
		enum msm_vfe_input_src frame_src)
		{
		msm_camera_io_w_mb(0xF, vfe_dev->vfe_base + 0x260);
		}
		@@ -723,21 +723,9 @@ static void msm_vfe32_axi_clear_wm_irq_mask(struct vfe_device *vfe_dev,
		}

		static void msm_vfe32_cfg_framedrop(struct vfe_device *vfe_dev,
		struct msm_vfe_axi_stream *stream_info)
		struct msm_vfe_axi_stream *stream_info, uint32_t framedrop_pattern,
		uint32_t framedrop_period)
		{
		uint32_t framedrop_pattern = 0, framedrop_period = 0;

		if (stream_info->runtime_init_frame_drop == 0) {
		framedrop_pattern = stream_info->framedrop_pattern;
		framedrop_period = stream_info->framedrop_period;
		}

		if (stream_info->stream_type == BURST_STREAM &&
		stream_info->runtime_burst_frame_count == 0) {
		framedrop_pattern = 0;
		framedrop_period = 0;
		}

		if (stream_info->stream_src == PIX_ENCODER) {
		msm_camera_io_w(framedrop_period, vfe_dev->vfe_base + 0x504);
		msm_camera_io_w(framedrop_period, vfe_dev->vfe_base + 0x508);
		@@ -1473,6 +1461,7 @@ struct msm_vfe_hardware_info vfe32_hw_info = {
		.process_reg_update = msm_vfe32_process_reg_update,
		.process_axi_irq = msm_isp_process_axi_irq,
		.process_stats_irq = msm_isp_process_stats_irq,
		.process_epoch_irq = msm_vfe32_process_epoch_irq,
		},
		.axi_ops = {
		.reload_wm = msm_vfe32_axi_reload_wm,

drivers/media/platform/msm/camera_v2/isp/msm_isp40.c

+120 −63

Original line number	Diff line number	Diff line
		@@ -436,9 +436,7 @@ static void msm_vfe40_process_input_irq(struct vfe_device *vfe_dev,
		uint32_t irq_status0, uint32_t irq_status1,
		struct msm_isp_timestamp *ts)
		{
		int cnt;

		if (!(irq_status0 & 0x100000F))
		if (!(irq_status0 & 0x1000003))
		return;

		if (irq_status0 & (1 << 24)) {
		@@ -447,23 +445,20 @@ static void msm_vfe40_process_input_irq(struct vfe_device *vfe_dev,
		&vfe_dev->fetch_engine_info);
		}

		if (irq_status0 & (1 << 0)) {
		if (irq_status0 & BIT(0)) {
		ISP_DBG("%s: SOF IRQ\n", __func__);
		cnt = vfe_dev->axi_data.src_info[VFE_PIX_0].raw_stream_count;
		if (cnt > 0) {
		msm_isp_sof_notify(vfe_dev, VFE_RAW_0, ts);
		if (vfe_dev->axi_data.stream_update)
		msm_isp_axi_stream_update(vfe_dev,
		(1 << VFE_RAW_0));
		msm_isp_update_framedrop_reg(vfe_dev, (1 << VFE_RAW_0));
		if (vfe_dev->axi_data.src_info[VFE_PIX_0].raw_stream_count > 0
		&& vfe_dev->axi_data.src_info[VFE_PIX_0].
		pix_stream_count == 0) {
		msm_isp_notify(vfe_dev, ISP_EVENT_SOF, VFE_PIX_0, ts);
		if (vfe_dev->axi_data.stream_update[VFE_PIX_0])
		msm_isp_axi_stream_update(vfe_dev, VFE_PIX_0);
		msm_isp_update_framedrop_reg(vfe_dev, VFE_PIX_0);
		}
		}

		if (irq_status0 & (1 << 1))
		ISP_DBG("%s: EOF IRQ\n", __func__);
		if (irq_status0 & (1 << 2))
		ISP_DBG("%s: EPOCH0 IRQ\n", __func__);
		if (irq_status0 & (1 << 3))
		ISP_DBG("%s: EPOCH1 IRQ\n", __func__);
		}

		static void msm_vfe40_process_violation_status(
		@@ -660,44 +655,96 @@ static void msm_vfe40_process_reg_update(struct vfe_device *vfe_dev,
		uint32_t irq_status0, uint32_t irq_status1,
		struct msm_isp_timestamp *ts)
		{
		uint8_t input_src = 0x0;
		enum msm_vfe_input_src i;
		uint32_t shift_irq;

		if (!(irq_status0 & 0xF0))
		return;

		if (irq_status0 & BIT(4)) {
		msm_isp_sof_notify(vfe_dev, VFE_PIX_0, ts);
		input_src \|= (1 << VFE_PIX_0);
		/* Shift status bits so that PIX REG UPDATE is 1st bit */
		shift_irq = ((irq_status0 & 0xF0) >> 4);

		for (i = VFE_PIX_0; i <= VFE_RAW_2; i++) {
		if (shift_irq & BIT(i)) {
		vfe_dev->axi_data.reg_update_requested &= ~BIT(i);
		ISP_DBG("%s update_mask %x\n", __func__,
		(uint32_t)BIT(i));
		switch (i) {
		case VFE_PIX_0:
		msm_isp_notify(vfe_dev, ISP_EVENT_REG_UPDATE,
		VFE_PIX_0, ts);
		if (atomic_read(
		&vfe_dev->stats_data.stats_update))
		msm_isp_stats_stream_update(vfe_dev);
		break;
		case VFE_RAW_0:
		case VFE_RAW_1:
		case VFE_RAW_2:
		msm_isp_notify(vfe_dev, ISP_EVENT_SOF, i, ts);
		msm_isp_update_framedrop_reg(vfe_dev, i);
		/*
		* Reg Update is pseudo SOF for RDI,
		* so request every frame
		*/
		vfe_dev->hw_info->vfe_ops.core_ops.reg_update(
		vfe_dev, i);
		break;
		default:
		pr_err("%s: Error case\n", __func__);
		return;
		}
		if (vfe_dev->axi_data.stream_update[i])
		msm_isp_axi_stream_update(vfe_dev, i);
		if (atomic_read(&vfe_dev->axi_data.axi_cfg_update[i])) {
		msm_isp_axi_cfg_update(vfe_dev, i);
		if (atomic_read(
		&vfe_dev->axi_data.axi_cfg_update[i]) ==
		0)
		msm_isp_notify(vfe_dev,
		ISP_EVENT_STREAM_UPDATE_DONE,
		i, ts);
		}
		if (irq_status0 & BIT(5)) {
		msm_isp_sof_notify(vfe_dev, VFE_RAW_0, ts);
		input_src \|= (1 << VFE_RAW_0);
		}
		if (irq_status0 & BIT(6)) {
		msm_isp_sof_notify(vfe_dev, VFE_RAW_1, ts);
		input_src \|= (1 << VFE_RAW_1);
		}
		if (irq_status0 & BIT(7)) {
		msm_isp_sof_notify(vfe_dev, VFE_RAW_2, ts);
		input_src \|= (1 << VFE_RAW_2);
		}

		if (vfe_dev->axi_data.stream_update)
		msm_isp_axi_stream_update(vfe_dev, input_src);
		if (atomic_read(&vfe_dev->stats_data.stats_update))
		msm_isp_stats_stream_update(vfe_dev);
		if (atomic_read(&vfe_dev->axi_data.axi_cfg_update))
		msm_isp_axi_cfg_update(vfe_dev);
		msm_isp_update_framedrop_reg(vfe_dev, input_src);
		msm_isp_update_stats_framedrop_reg(vfe_dev);
		msm_isp_update_error_frame_count(vfe_dev);

		vfe_dev->hw_info->vfe_ops.core_ops.reg_update(vfe_dev);
		static void msm_vfe40_reg_update(struct vfe_device *vfe_dev,
		enum msm_vfe_input_src frame_src)
		{
		uint32_t update_mask = 0;
		/* This HW supports upto VFE_RAW_2 */
		if (frame_src > VFE_RAW_2 && frame_src != VFE_SRC_MAX) {
		pr_err("%s Error case\n", __func__);
		return;
		}

		static void msm_vfe40_reg_update(struct vfe_device *vfe_dev)
		/*
		* If frame_src == VFE_SRC_MAX request reg_update on all
		* supported INTF
		*/
		if (frame_src == VFE_SRC_MAX)
		update_mask = 0xF;
		else
		update_mask = BIT((uint32_t)frame_src);
		ISP_DBG("%s update_mask %x\n", __func__, update_mask);
		vfe_dev->axi_data.reg_update_requested \|= update_mask;
		msm_camera_io_w_mb(vfe_dev->axi_data.reg_update_requested,
		vfe_dev->vfe_base + 0x378);
		}

		static void msm_vfe40_process_epoch_irq(struct vfe_device *vfe_dev,
		uint32_t irq_status0, uint32_t irq_status1,
		struct msm_isp_timestamp *ts)
		{
		msm_camera_io_w_mb(0xF, vfe_dev->vfe_base + 0x378);
		if (!(irq_status0 & 0xc))
		return;

		if (irq_status0 & BIT(2)) {
		msm_isp_notify(vfe_dev, ISP_EVENT_SOF, VFE_PIX_0, ts);
		ISP_DBG("%s: EPOCH0 IRQ\n", __func__);
		msm_isp_update_framedrop_reg(vfe_dev, VFE_PIX_0);
		msm_isp_update_stats_framedrop_reg(vfe_dev);
		msm_isp_update_error_frame_count(vfe_dev);
		}
		}

		static long msm_vfe40_reset_hardware(struct vfe_device *vfe_dev,
		@@ -846,21 +893,10 @@ static void msm_vfe40_axi_clear_wm_irq_mask(struct vfe_device *vfe_dev,
		}

		static void msm_vfe40_cfg_framedrop(struct vfe_device *vfe_dev,
		struct msm_vfe_axi_stream *stream_info)
		struct msm_vfe_axi_stream *stream_info, uint32_t framedrop_pattern,
		uint32_t framedrop_period)
		{
		uint32_t i, temp;
		uint32_t framedrop_pattern = 0, framedrop_period = 0;

		if (stream_info->runtime_init_frame_drop == 0) {
		framedrop_pattern = stream_info->framedrop_pattern;
		framedrop_period = stream_info->framedrop_period;
		}

		if (stream_info->stream_type == BURST_STREAM &&
		stream_info->runtime_burst_frame_count == 0) {
		framedrop_pattern = 0;
		framedrop_period = 0;
		}

		for (i = 0; i < stream_info->num_planes; i++) {
		msm_camera_io_w(framedrop_pattern, vfe_dev->vfe_base +
		@@ -1106,7 +1142,6 @@ static void msm_vfe40_cfg_fetch_engine(struct vfe_device *vfe_dev,
		msm_camera_io_w(0xF6543210, vfe_dev->vfe_base + 0x248);
		msm_camera_io_w(0xF, vfe_dev->vfe_base + 0x264);

		vfe_dev->hw_info->vfe_ops.core_ops.reg_update(vfe_dev);
		return;
		}

		@@ -1498,6 +1533,7 @@ static int msm_vfe40_axi_halt(struct vfe_device *vfe_dev,
		uint32_t blocking)
		{
		int rc = 0;
		enum msm_vfe_input_src i;

		/* Keep only halt and restart mask */
		msm_camera_io_w(BIT(31), vfe_dev->vfe_base + 0x28);
		@@ -1507,10 +1543,30 @@ static int msm_vfe40_axi_halt(struct vfe_device *vfe_dev,
		msm_camera_io_w(0xFEFFFEFF, vfe_dev->vfe_base + 0x34);
		msm_camera_io_w(0x1, vfe_dev->vfe_base + 0x24);
		/* if any stream is waiting for update, signal complete */
		if (vfe_dev->axi_data.stream_update) {
		pr_err("%s: calling complete on stream update\n", __func__);
		complete(&vfe_dev->stream_config_complete);
		for (i = VFE_PIX_0; i <= VFE_RAW_2; i++) {
		/* if any stream is waiting for update, signal complete */
		if (vfe_dev->axi_data.stream_update[i]) {
		ISP_DBG("%s: complete stream update\n", __func__);
		msm_isp_axi_stream_update(vfe_dev, i);
		if (vfe_dev->axi_data.stream_update[i])
		msm_isp_axi_stream_update(vfe_dev, i);
		}
		if (atomic_read(&vfe_dev->axi_data.axi_cfg_update[i])) {
		ISP_DBG("%s: complete on axi config update\n",
		__func__);
		msm_isp_axi_cfg_update(vfe_dev, i);
		if (atomic_read(&vfe_dev->axi_data.axi_cfg_update[i]))
		msm_isp_axi_cfg_update(vfe_dev, i);
		}
		}

		if (atomic_read(&vfe_dev->stats_data.stats_update)) {
		ISP_DBG("%s: complete on stats update\n", __func__);
		msm_isp_stats_stream_update(vfe_dev);
		if (atomic_read(&vfe_dev->stats_data.stats_update))
		msm_isp_stats_stream_update(vfe_dev);
		}

		if (blocking) {
		init_completion(&vfe_dev->halt_complete);
		/* Halt AXI Bus Bridge */
		@@ -1537,7 +1593,7 @@ static int msm_vfe40_axi_restart(struct vfe_device *vfe_dev,
		/* Start AXI */
		msm_camera_io_w(0x0, vfe_dev->vfe_base + 0x2C0);

		vfe_dev->hw_info->vfe_ops.core_ops.reg_update(vfe_dev);
		vfe_dev->hw_info->vfe_ops.core_ops.reg_update(vfe_dev, VFE_SRC_MAX);
		memset(&vfe_dev->error_info, 0, sizeof(vfe_dev->error_info));
		atomic_set(&vfe_dev->error_info.overflow_state, NO_OVERFLOW);

		@@ -2000,6 +2056,7 @@ struct msm_vfe_hardware_info vfe40_hw_info = {
		.process_reg_update = msm_vfe40_process_reg_update,
		.process_axi_irq = msm_isp_process_axi_irq,
		.process_stats_irq = msm_isp_process_stats_irq,
		.process_epoch_irq = msm_vfe40_process_epoch_irq,
		},
		.axi_ops = {
		.reload_wm = msm_vfe40_axi_reload_wm,

drivers/media/platform/msm/camera_v2/isp/msm_isp44.c

+110 −72

Original line number	Diff line number	Diff line
		@@ -288,7 +288,7 @@ static void msm_vfe44_process_input_irq(struct vfe_device *vfe_dev,
		uint32_t irq_status0, uint32_t irq_status1,
		struct msm_isp_timestamp *ts)
		{
		if (!(irq_status0 & 0x100000F))
		if (!(irq_status0 & 0x1000003))
		return;

		if (irq_status0 & (1 << 24)) {
		@@ -298,23 +298,19 @@ static void msm_vfe44_process_input_irq(struct vfe_device *vfe_dev,
		}

		if (irq_status0 & (1 << 0)) {
		ISP_DBG("%s: SOF IRQ\n", __func__);
		if (vfe_dev->axi_data.src_info[VFE_PIX_0].raw_stream_count > 0
		&& vfe_dev->axi_data.src_info[VFE_PIX_0].
		pix_stream_count == 0) {
		msm_isp_sof_notify(vfe_dev, VFE_PIX_0, ts);
		if (vfe_dev->axi_data.stream_update)
		msm_isp_axi_stream_update(vfe_dev,
		(1 << VFE_PIX_0));
		msm_isp_update_framedrop_reg(vfe_dev, (1 << VFE_PIX_0));
		ISP_DBG("%s: SOF IRQ\n", __func__);
		msm_isp_notify(vfe_dev, ISP_EVENT_SOF, VFE_PIX_0, ts);
		if (vfe_dev->axi_data.stream_update[VFE_PIX_0])
		msm_isp_axi_stream_update(vfe_dev, VFE_PIX_0);
		msm_isp_update_framedrop_reg(vfe_dev, VFE_PIX_0);
		}
		}

		if (irq_status0 & (1 << 1))
		ISP_DBG("%s: EOF IRQ\n", __func__);
		if (irq_status0 & (1 << 2))
		ISP_DBG("%s: EPOCH0 IRQ\n", __func__);
		if (irq_status0 & (1 << 3))
		ISP_DBG("%s: EPOCH1 IRQ\n", __func__);
		}

		static void msm_vfe44_process_violation_status(
		@@ -501,44 +497,95 @@ static void msm_vfe44_process_reg_update(struct vfe_device *vfe_dev,
		uint32_t irq_status0, uint32_t irq_status1,
		struct msm_isp_timestamp *ts)
		{
		uint8_t input_src = 0x0;
		enum msm_vfe_input_src i;
		uint32_t shift_irq;

		if (!(irq_status0 & 0xF0))
		return;

		if (irq_status0 & BIT(4)) {
		msm_isp_sof_notify(vfe_dev, VFE_PIX_0, ts);
		input_src \|= (1 << VFE_PIX_0);
		/* Shift status bits so that PIX SOF is 1st bit */
		shift_irq = ((irq_status0 & 0xF0) >> 4);

		for (i = VFE_PIX_0; i <= VFE_RAW_2; i++) {
		if (shift_irq & BIT(i)) {
		vfe_dev->axi_data.reg_update_requested &= ~BIT(i);
		ISP_DBG("%s update_mask %x\n", __func__,
		(uint32_t)BIT(i));
		switch (i) {
		case VFE_PIX_0:
		msm_isp_notify(vfe_dev, ISP_EVENT_REG_UPDATE,
		VFE_PIX_0, ts);
		if (atomic_read(
		&vfe_dev->stats_data.stats_update))
		msm_isp_stats_stream_update(vfe_dev);
		break;
		case VFE_RAW_0:
		case VFE_RAW_1:
		case VFE_RAW_2:
		msm_isp_notify(vfe_dev, ISP_EVENT_SOF, i, ts);
		msm_isp_update_framedrop_reg(vfe_dev, i);
		/*
		* Reg Update is pseudo SOF for RDI,
		* so request every frame
		*/
		vfe_dev->hw_info->vfe_ops.core_ops.reg_update(
		vfe_dev, i);
		break;
		default:
		pr_err("%s: Error case\n", __func__);
		return;
		}
		if (vfe_dev->axi_data.stream_update[i])
		msm_isp_axi_stream_update(vfe_dev, i);
		if (atomic_read(&vfe_dev->axi_data.axi_cfg_update[i])) {
		msm_isp_axi_cfg_update(vfe_dev, i);
		if (atomic_read(
		&vfe_dev->axi_data.axi_cfg_update[i]) ==
		0)
		msm_isp_notify(vfe_dev,
		ISP_EVENT_STREAM_UPDATE_DONE,
		i, ts);
		}
		if (irq_status0 & BIT(5)) {
		msm_isp_sof_notify(vfe_dev, VFE_RAW_0, ts);
		input_src \|= (1 << VFE_RAW_0);
		}
		if (irq_status0 & BIT(6)) {
		msm_isp_sof_notify(vfe_dev, VFE_RAW_1, ts);
		input_src \|= (1 << VFE_RAW_1);
		}
		if (irq_status0 & BIT(7)) {
		msm_isp_sof_notify(vfe_dev, VFE_RAW_2, ts);
		input_src \|= (1 << VFE_RAW_2);
		}

		if (vfe_dev->axi_data.stream_update)
		msm_isp_axi_stream_update(vfe_dev, input_src);
		if (atomic_read(&vfe_dev->stats_data.stats_update))
		msm_isp_stats_stream_update(vfe_dev);
		if (atomic_read(&vfe_dev->axi_data.axi_cfg_update))
		msm_isp_axi_cfg_update(vfe_dev);
		static void msm_vfe44_process_epoch_irq(struct vfe_device *vfe_dev,
		uint32_t irq_status0, uint32_t irq_status1,
		struct msm_isp_timestamp *ts)
		{
		if (!(irq_status0 & 0xc))
		return;

		msm_isp_update_framedrop_reg(vfe_dev, input_src);
		if (irq_status0 & BIT(2)) {
		msm_isp_notify(vfe_dev, ISP_EVENT_SOF, VFE_PIX_0, ts);
		ISP_DBG("%s: EPOCH0 IRQ\n", __func__);
		msm_isp_update_framedrop_reg(vfe_dev, VFE_PIX_0);
		msm_isp_update_stats_framedrop_reg(vfe_dev);
		msm_isp_update_error_frame_count(vfe_dev);

		vfe_dev->hw_info->vfe_ops.core_ops.reg_update(vfe_dev);
		}
		}

		static void msm_vfe44_reg_update(struct vfe_device *vfe_dev)
		static void msm_vfe44_reg_update(struct vfe_device *vfe_dev,
		enum msm_vfe_input_src frame_src)
		{
		msm_camera_io_w_mb(0xF, vfe_dev->vfe_base + 0x378);
		uint32_t update_mask = 0;
		/* This HW supports upto VFE_RAW_2 */
		if (frame_src > VFE_RAW_2 && frame_src != VFE_SRC_MAX) {
		pr_err("%s Error case\n", __func__);
		return;
		}

		/*
		* If frame_src == VFE_SRC_MAX request reg_update on
		* all supported INTF
		*/
		if (frame_src == VFE_SRC_MAX)
		update_mask = 0xF;
		else
		update_mask = BIT((uint32_t)frame_src);
		vfe_dev->axi_data.reg_update_requested \|= update_mask;
		msm_camera_io_w_mb(vfe_dev->axi_data.reg_update_requested,
		vfe_dev->vfe_base + 0x378);
		}

		static long msm_vfe44_reset_hardware(struct vfe_device *vfe_dev,
		@@ -660,21 +707,10 @@ static void msm_vfe44_axi_clear_wm_irq_mask(struct vfe_device *vfe_dev,
		}

		static void msm_vfe44_cfg_framedrop(struct vfe_device *vfe_dev,
		struct msm_vfe_axi_stream *stream_info)
		struct msm_vfe_axi_stream *stream_info, uint32_t framedrop_pattern,
		uint32_t framedrop_period)
		{
		uint32_t i, temp;
		uint32_t framedrop_pattern = 0, framedrop_period = 0;

		if (stream_info->runtime_init_frame_drop == 0) {
		framedrop_pattern = stream_info->framedrop_pattern;
		framedrop_period = stream_info->framedrop_period;
		}

		if (stream_info->stream_type == BURST_STREAM &&
		stream_info->runtime_burst_frame_count == 0) {
		framedrop_pattern = 0;
		framedrop_period = 0;
		}

		for (i = 0; i < stream_info->num_planes; i++) {
		msm_camera_io_w(framedrop_pattern, vfe_dev->vfe_base +
		@@ -685,8 +721,6 @@ static void msm_vfe44_cfg_framedrop(struct vfe_device *vfe_dev,
		msm_camera_io_w(temp \| framedrop_period << 2,
		vfe_dev->vfe_base + VFE44_WM_BASE(stream_info->wm[i]) + 0xC);
		}

		msm_camera_io_w_mb(0x1, vfe_dev->vfe_base + 0x378);
		}

		static void msm_vfe44_clear_framedrop(struct vfe_device *vfe_dev,
		@@ -920,7 +954,6 @@ static void msm_vfe44_cfg_fetch_engine(struct vfe_device *vfe_dev,
		temp \|= 2 << 16 \| pix_cfg->pixel_pattern;
		msm_camera_io_w(temp, vfe_dev->vfe_base + 0x1C);

		vfe_dev->hw_info->vfe_ops.core_ops.reg_update(vfe_dev);
		} else {
		pr_err("%s: Invalid mux configuration - mux: %d", __func__,
		pix_cfg->input_mux);
		@@ -1007,7 +1040,7 @@ static void msm_vfe44_update_camif_state(struct vfe_device *vfe_dev,

		if (update_state == ENABLE_CAMIF) {
		val = msm_camera_io_r(vfe_dev->vfe_base + 0x28);
		val \|= 0xF1;
		val \|= 0xF5;
		msm_camera_io_w_mb(val, vfe_dev->vfe_base + 0x28);

		bus_en =
		@@ -1022,6 +1055,7 @@ static void msm_vfe44_update_camif_state(struct vfe_device *vfe_dev,
		msm_camera_io_w(val, vfe_dev->vfe_base + 0x2F8);
		msm_camera_io_w_mb(0x4, vfe_dev->vfe_base + 0x2F4);
		msm_camera_io_w_mb(0x1, vfe_dev->vfe_base + 0x2F4);
		msm_camera_io_w_mb(0x200, vfe_dev->vfe_base + 0x318);
		vfe_dev->axi_data.src_info[VFE_PIX_0].active = 1;
		} else if (update_state == DISABLE_CAMIF) {
		msm_camera_io_w_mb(0x0, vfe_dev->vfe_base + 0x2F4);
		@@ -1264,6 +1298,7 @@ static int msm_vfe44_axi_halt(struct vfe_device *vfe_dev,
		uint32_t blocking)
		{
		int rc = 0;
		enum msm_vfe_input_src i;

		/* Keep only halt and restart mask */
		msm_camera_io_w(BIT(31), vfe_dev->vfe_base + 0x28);
		@@ -1289,12 +1324,21 @@ static int msm_vfe44_axi_halt(struct vfe_device *vfe_dev,
		msm_camera_io_w_mb(0x1, vfe_dev->vfe_base + 0x2C0);
		}

		for (i = VFE_PIX_0; i <= VFE_RAW_2; i++) {
		/* if any stream is waiting for update, signal complete */
		if (vfe_dev->axi_data.stream_update) {
		if (vfe_dev->axi_data.stream_update[i]) {
		ISP_DBG("%s: complete stream update\n", __func__);
		msm_isp_axi_stream_update(vfe_dev, 0xF);
		if (vfe_dev->axi_data.stream_update)
		msm_isp_axi_stream_update(vfe_dev, 0xF);
		msm_isp_axi_stream_update(vfe_dev, i);
		if (vfe_dev->axi_data.stream_update[i])
		msm_isp_axi_stream_update(vfe_dev, i);
		}
		if (atomic_read(&vfe_dev->axi_data.axi_cfg_update[i])) {
		ISP_DBG("%s: complete on axi config update\n",
		__func__);
		msm_isp_axi_cfg_update(vfe_dev, i);
		if (atomic_read(&vfe_dev->axi_data.axi_cfg_update[i]))
		msm_isp_axi_cfg_update(vfe_dev, i);
		}
		}

		if (atomic_read(&vfe_dev->stats_data.stats_update)) {
		@@ -1304,13 +1348,6 @@ static int msm_vfe44_axi_halt(struct vfe_device *vfe_dev,
		msm_isp_stats_stream_update(vfe_dev);
		}

		if (atomic_read(&vfe_dev->axi_data.axi_cfg_update)) {
		ISP_DBG("%s: complete on axi config update\n", __func__);
		msm_isp_axi_cfg_update(vfe_dev);
		if (atomic_read(&vfe_dev->axi_data.axi_cfg_update))
		msm_isp_axi_cfg_update(vfe_dev);
		}

		return rc;
		}

		@@ -1325,7 +1362,7 @@ static int msm_vfe44_axi_restart(struct vfe_device *vfe_dev,
		/* Start AXI */
		msm_camera_io_w(0x0, vfe_dev->vfe_base + 0x2C0);

		vfe_dev->hw_info->vfe_ops.core_ops.reg_update(vfe_dev);
		vfe_dev->hw_info->vfe_ops.core_ops.reg_update(vfe_dev, VFE_SRC_MAX);
		memset(&vfe_dev->error_info, 0, sizeof(vfe_dev->error_info));
		atomic_set(&vfe_dev->error_info.overflow_state, NO_OVERFLOW);

		@@ -1839,6 +1876,7 @@ struct msm_vfe_hardware_info vfe44_hw_info = {
		.process_reg_update = msm_vfe44_process_reg_update,
		.process_axi_irq = msm_isp_process_axi_irq,
		.process_stats_irq = msm_isp_process_stats_irq,
		.process_epoch_irq = msm_vfe44_process_epoch_irq,
		},
		.axi_ops = {
		.reload_wm = msm_vfe44_axi_reload_wm,

drivers/media/platform/msm/camera_v2/isp/msm_isp46.c

+112 −70

File changed.

Preview size limit exceeded, changes collapsed.