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Commit 5cbea2d7 authored by Taniya Das's avatar Taniya Das
Browse files

ARM: dts: msm: Limit DDR to 200MHz for APSS frequency 



For APSS frequency of 787MHz, DDR frequency still required to be at SVS of
BIMC frequency.

CRs-Fixed: 644461
Change-Id: If129291f544adec30792ca20bfbfefb44141ef53
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 6ddb099c

arch/arm/boot/dts/qcom/msm8226.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -1004,7 +1004,7 @@ 
			<  300000 1525 >,

			<  384000 1525 >,

			<  600000 1525 >,

			<  787200 3051 >,

			<  787200 1525 >,

			<  998400 4066 >,

			< 1094400 4066 >,

			< 1190400 4066 >,