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Commit 5b912fe0 authored by Taniya Das's avatar Taniya Das
Browse files

ARM: dts: msm: Add support for 1.1GHz for 8610 



A new speed bin has been added to identify 1.1GHz, add the same for
version 0 and version 2 of MSM8610.

Change-Id: I06e5bc7e000dfc16117ae188a76a3c54a3390cc8
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 77484ca1

arch/arm/boot/dts/qcom/msm8610-v2.dtsi

+17 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2013, The Linux Foundation. All rights reserved.

/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -24,3 +24,19 @@ 
				  <163 0x10001>, <164 0x10001>, <166 0x10001>,

                                  <225 0x10001>, <226 0x10001>;

};



&soc {

	qcom,clock-a7@f9011050 {

		compatible = "qcom,clock-a7-8226";

		reg = <0xf9011050 0x8>,

		      <0xfc4b80b8 0x8>;

		reg-names = "rcg-base", "efuse";

		clock-names = "clk-4", "clk-5";

		qcom,speed1-bin-v2 =

			<         0 0>,

			< 384000000 1>,

			< 787200000 2>,

			<1094400000 3>;

	};

};

arch/arm/boot/dts/qcom/msm8610.dtsi

+9 −2
Original line number Diff line number Diff line
@@ -506,14 +506,20 @@ 


	qcom,clock-a7@f9011050 {

		compatible = "qcom,clock-a7-8226";

		reg = <0xf9011050 0x8>;

		reg-names = "rcg-base";

		reg = <0xf9011050 0x8>,

		      <0xfc4b80b8 0x8>;

		reg-names = "rcg-base", "efuse";

		clock-names = "clk-4", "clk-5";

		qcom,speed0-bin-v0 =

			<         0 0>,

			< 384000000 1>,

			< 787200000 2>,

			<1190400000 3>;

		qcom,speed1-bin-v0 =

			<         0 0>,

			< 384000000 1>,

			< 787200000 2>,

			<1094400000 3>;



		cpu-vdd-supply = <&apc_vreg_corner>;

	};
@@ -546,6 +552,7 @@ 
			<  600000 >,

			<  787200 >,

			<  998400 >,

			< 1094400 >,

			< 1190400 >;

	};