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Commit 5a717b7d authored by Megha Tak's avatar Megha Tak
Browse files

msm-camera: Reset ISPIF h/w 



Reseting ISPIF hardware after ISPIF is stopped without frame
boundaries.Enabling all clocks for same.

Change-Id: I3712a2af9a3011769e14fab14ddaa5a32f6bcb90
Signed-off-by: default avatarMegha Tak <mtak@codeaurora.org>
parent 4e31a3a1

arch/arm/mach-msm/clock-8226.c

+29 −1
Original line number Diff line number Diff line
@@ -3436,8 +3436,36 @@ static struct clk_lookup msm_clocks_8226[] = { 
					"fda08400.qcom,csid"),



	/* ISPIF clocks */



	CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,

					"fda0a000.qcom,ispif"),

	CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,

					"fda0a000.qcom,ispif"),

	CLK_LOOKUP("csi0_ahb_clk", camss_csi0_ahb_clk.c,

					"fda0a000.qcom,ispif"),

	CLK_LOOKUP("csi0_src_clk", csi0_clk_src.c,

					"fda0a000.qcom,ispif"),

	CLK_LOOKUP("csi0_phy_clk", camss_csi0phy_clk.c,

					"fda0a000.qcom,ispif"),

	CLK_LOOKUP("csi0_clk", camss_csi0_clk.c,

					"fda0a000.qcom,ispif"),

	CLK_LOOKUP("csi0_pix_clk", camss_csi0pix_clk.c,

					"fda0a000.qcom,ispif"),

	CLK_LOOKUP("csi0_rdi_clk", camss_csi0rdi_clk.c,

					"fda0a000.qcom,ispif"),



	CLK_LOOKUP("csi1_ahb_clk", camss_csi1_ahb_clk.c,

					"fda0a000.qcom,ispif"),

	CLK_LOOKUP("csi1_src_clk", csi1_clk_src.c,

					"fda0a000.qcom,ispif"),

	CLK_LOOKUP("csi1_phy_clk", camss_csi1phy_clk.c,

					"fda0a000.qcom,ispif"),

	CLK_LOOKUP("csi1_clk", camss_csi1_clk.c,

					"fda0a000.qcom,ispif"),

	CLK_LOOKUP("csi1_pix_clk", camss_csi1pix_clk.c,

					"fda0a000.qcom,ispif"),

	CLK_LOOKUP("csi1_rdi_clk", camss_csi1rdi_clk.c,

					"fda0a000.qcom,ispif"),

	CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c,

		"fda0a000.qcom,ispif"),

	CLK_LOOKUP("camss_csi_vfe_clk", camss_csi_vfe0_clk.c,

drivers/media/platform/msm/camera_v2/ispif/msm_ispif.c

+64 −14
Original line number Diff line number Diff line
@@ -65,6 +65,25 @@ static inline int msm_ispif_is_intf_valid(uint32_t csid_version, 
		false : true;

}



static struct msm_cam_clk_info ispif_8626_reset_clk_info[] = {

	{"ispif_ahb_clk", NO_SET_RATE},

	{"camss_top_ahb_clk", NO_SET_RATE},

	{"csi0_ahb_clk", NO_SET_RATE},

	{"csi0_src_clk", NO_SET_RATE},

	{"csi0_phy_clk", NO_SET_RATE},

	{"csi0_clk", NO_SET_RATE},

	{"csi0_pix_clk", NO_SET_RATE},

	{"csi0_rdi_clk", NO_SET_RATE},

	{"csi1_ahb_clk", NO_SET_RATE},

	{"csi1_src_clk", NO_SET_RATE},

	{"csi1_phy_clk", NO_SET_RATE},

	{"csi1_clk", NO_SET_RATE},

	{"csi1_pix_clk", NO_SET_RATE},

	{"csi1_rdi_clk", NO_SET_RATE},

	{"camss_vfe_vfe_clk", NO_SET_RATE},

	{"camss_csi_vfe_clk", NO_SET_RATE},

};



static struct msm_cam_clk_info ispif_8974_ahb_clk_info[ISPIF_CLK_INFO_MAX];



static struct msm_cam_clk_info ispif_8974_reset_clk_info[] = {
@@ -97,13 +116,26 @@ static int msm_ispif_reset_hw(struct ispif_device *ispif) 
	int rc = 0;

	long timeout = 0;

	struct clk *reset_clk[ARRAY_SIZE(ispif_8974_reset_clk_info)];

	struct clk *reset_clk1[ARRAY_SIZE(ispif_8626_reset_clk_info)];

	ispif->clk_idx = 0;



	rc = msm_cam_clk_enable(&ispif->pdev->dev,

		ispif_8974_reset_clk_info, reset_clk,

		ARRAY_SIZE(ispif_8974_reset_clk_info), 1);

	if (rc < 0) {

		rc = msm_cam_clk_enable(&ispif->pdev->dev,

			ispif_8626_reset_clk_info, reset_clk1,

			ARRAY_SIZE(ispif_8626_reset_clk_info), 1);

		if (rc < 0) {

			pr_err("%s: cannot enable clock, error = %d",

				__func__, rc);

		} else {

			/* This is set when device is 8x26 */

			ispif->clk_idx = 2;

		}

	} else {

		/* This is set when device is 8974 */

		ispif->clk_idx = 1;

	}



	init_completion(&ispif->reset_complete[VFE0]);
@@ -120,11 +152,20 @@ static int msm_ispif_reset_hw(struct ispif_device *ispif) 
	timeout = wait_for_completion_timeout(

			&ispif->reset_complete[VFE0], msecs_to_jiffies(500));

	CDBG("%s: VFE0 done\n", __func__);



	if (timeout <= 0) {

		pr_err("%s: VFE0 reset wait timeout\n", __func__);

		msm_cam_clk_enable(&ispif->pdev->dev,

		rc = msm_cam_clk_enable(&ispif->pdev->dev,

			ispif_8974_reset_clk_info, reset_clk,

			ARRAY_SIZE(ispif_8974_reset_clk_info), 0);

		if (rc < 0) {

			rc = msm_cam_clk_enable(&ispif->pdev->dev,

				ispif_8626_reset_clk_info, reset_clk1,

				ARRAY_SIZE(ispif_8626_reset_clk_info), 0);

			if (rc < 0)

				pr_err("%s: VFE0 reset wait timeout\n",

					 __func__);

		}

		return -ETIMEDOUT;

	}
@@ -142,6 +183,7 @@ static int msm_ispif_reset_hw(struct ispif_device *ispif) 
		}

	}



	if (ispif->clk_idx == 1) {

		rc = msm_cam_clk_enable(&ispif->pdev->dev,

			ispif_8974_reset_clk_info, reset_clk,

			ARRAY_SIZE(ispif_8974_reset_clk_info), 0);
@@ -149,6 +191,18 @@ static int msm_ispif_reset_hw(struct ispif_device *ispif) 
			pr_err("%s: cannot disable clock, error = %d",

				__func__, rc);

		}

	}



	if (ispif->clk_idx == 2) {

		rc = msm_cam_clk_enable(&ispif->pdev->dev,

			ispif_8626_reset_clk_info, reset_clk1,

			ARRAY_SIZE(ispif_8626_reset_clk_info), 0);

		if (rc < 0) {

			pr_err("%s: cannot disable clock, error = %d",

				__func__, rc);

		}

	}



	return rc;

}
@@ -996,11 +1050,7 @@ static int msm_ispif_init(struct ispif_device *ispif, 
		goto error_ahb;

	}



	if (of_device_is_compatible(ispif->pdev->dev.of_node,

				    "qcom,ispif-v3.0")) {

		/* currently HW reset is implemented for 8974 only */

	msm_ispif_reset_hw(ispif);

	}



	rc = msm_ispif_reset(ispif);

	if (rc == 0) {

drivers/media/platform/msm/camera_v2/ispif/msm_ispif.h

+1 −0
Original line number Diff line number Diff line
@@ -63,5 +63,6 @@ struct ispif_device { 
	struct completion reset_complete[VFE_MAX];

	uint32_t hw_num_isps;

	uint32_t num_clk;

	uint32_t clk_idx;

};

#endif