Loading drivers/gpu/msm/adreno_a4xx.c +8 −2 Original line number Diff line number Diff line Loading @@ -668,6 +668,7 @@ static void a4xx_start(struct adreno_device *adreno_dev) { struct kgsl_device *device = &adreno_dev->dev; struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); unsigned int cp_debug = A4XX_CP_DEBUG_DEFAULT; adreno_vbif_start(adreno_dev, a4xx_vbif_platforms, ARRAY_SIZE(a4xx_vbif_platforms)); Loading Loading @@ -719,8 +720,13 @@ static void a4xx_start(struct adreno_device *adreno_dev) kgsl_regwrite(device, UCHE_TRAP_BASE_HI, 0xffff0000); /* On A420 cores turn on SKIP_IB2_DISABLE in addition to the default */ kgsl_regwrite(device, A4XX_CP_DEBUG, A4XX_CP_DEBUG_DEFAULT | (adreno_is_a420(adreno_dev) ? (1 << 29) : 0)); if (adreno_is_a420(adreno_dev)) cp_debug |= (1 << 29); /* Set chicken bit to disable the speed up of bootstrap on A430 */ else if (adreno_is_a430(adreno_dev)) cp_debug |= (1 << 14); kgsl_regwrite(device, A4XX_CP_DEBUG, cp_debug); /* On A430 enable SP regfile sleep for power savings */ if (!adreno_is_a420(adreno_dev)) { Loading drivers/gpu/msm/adreno_ringbuffer.c +9 −1 Original line number Diff line number Diff line Loading @@ -371,6 +371,7 @@ static int _ringbuffer_bootstrap_ucode(struct adreno_ringbuffer *rb, { unsigned int *cmds, bootstrap_size, rb_size; int i = 0; int ret; struct kgsl_device *device = rb->device; struct adreno_device *adreno_dev = ADRENO_DEVICE(device); unsigned int pm4_size, pm4_idx, pm4_addr, pfp_size, pfp_idx, pfp_addr; Loading Loading @@ -474,7 +475,14 @@ static int _ringbuffer_bootstrap_ucode(struct adreno_ringbuffer *rb, } /* idle device to validate bootstrap */ return adreno_spin_idle(device); ret = adreno_spin_idle(device); /* Clear the chicken bit for speed up on A430 cores */ if (adreno_is_a430(adreno_dev)) kgsl_regwrite(device, A4XX_CP_DEBUG, A4XX_CP_DEBUG_DEFAULT & ~(1 << 14)); return ret; } /** Loading Loading
drivers/gpu/msm/adreno_a4xx.c +8 −2 Original line number Diff line number Diff line Loading @@ -668,6 +668,7 @@ static void a4xx_start(struct adreno_device *adreno_dev) { struct kgsl_device *device = &adreno_dev->dev; struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); unsigned int cp_debug = A4XX_CP_DEBUG_DEFAULT; adreno_vbif_start(adreno_dev, a4xx_vbif_platforms, ARRAY_SIZE(a4xx_vbif_platforms)); Loading Loading @@ -719,8 +720,13 @@ static void a4xx_start(struct adreno_device *adreno_dev) kgsl_regwrite(device, UCHE_TRAP_BASE_HI, 0xffff0000); /* On A420 cores turn on SKIP_IB2_DISABLE in addition to the default */ kgsl_regwrite(device, A4XX_CP_DEBUG, A4XX_CP_DEBUG_DEFAULT | (adreno_is_a420(adreno_dev) ? (1 << 29) : 0)); if (adreno_is_a420(adreno_dev)) cp_debug |= (1 << 29); /* Set chicken bit to disable the speed up of bootstrap on A430 */ else if (adreno_is_a430(adreno_dev)) cp_debug |= (1 << 14); kgsl_regwrite(device, A4XX_CP_DEBUG, cp_debug); /* On A430 enable SP regfile sleep for power savings */ if (!adreno_is_a420(adreno_dev)) { Loading
drivers/gpu/msm/adreno_ringbuffer.c +9 −1 Original line number Diff line number Diff line Loading @@ -371,6 +371,7 @@ static int _ringbuffer_bootstrap_ucode(struct adreno_ringbuffer *rb, { unsigned int *cmds, bootstrap_size, rb_size; int i = 0; int ret; struct kgsl_device *device = rb->device; struct adreno_device *adreno_dev = ADRENO_DEVICE(device); unsigned int pm4_size, pm4_idx, pm4_addr, pfp_size, pfp_idx, pfp_addr; Loading Loading @@ -474,7 +475,14 @@ static int _ringbuffer_bootstrap_ucode(struct adreno_ringbuffer *rb, } /* idle device to validate bootstrap */ return adreno_spin_idle(device); ret = adreno_spin_idle(device); /* Clear the chicken bit for speed up on A430 cores */ if (adreno_is_a430(adreno_dev)) kgsl_regwrite(device, A4XX_CP_DEBUG, A4XX_CP_DEBUG_DEFAULT & ~(1 << 14)); return ret; } /** Loading