msm: gdsc: Make enable/disable function clock controls symmetric

Currently, resets are asserted and de-asserted in the same order,
which works fine for cores with only one resettable clock domain,
but causes issues on 8x10 (VFE) where multiple clock domains are
resettable and order matters.

For cleanliness, also make the order of setting/clearing the memory
retention signals symmetric, although order there doesn't matter
at all.

Change-Id: I0d5edcd0d9fe121ed63e032915830a9c82ae5da2
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>