Loading drivers/clk/qcom/clock-cpu-8994.c +2 −0 Original line number Diff line number Diff line Loading @@ -682,6 +682,7 @@ static struct alpha_pll_masks alpha_pll_masks_20nm_p = { .vco_mask = BM(21, 20) >> 20, .vco_shift = 20, .alpha_en_mask = BIT(24), .output_mask = 0xF, }; static struct alpha_pll_vco_tbl alpha_pll_vco_20nm_p[] = { Loading @@ -693,6 +694,7 @@ static struct alpha_pll_clk cci_pll = { .base = &vbases[CCI_PLL_BASE], .vco_tbl = alpha_pll_vco_20nm_p, .num_vco = ARRAY_SIZE(alpha_pll_vco_20nm_p), .enable_config = 0x9, /* Main and early outputs */ .c = { .parent = &xo_ao.c, .dbg_name = "cci_pll", Loading Loading
drivers/clk/qcom/clock-cpu-8994.c +2 −0 Original line number Diff line number Diff line Loading @@ -682,6 +682,7 @@ static struct alpha_pll_masks alpha_pll_masks_20nm_p = { .vco_mask = BM(21, 20) >> 20, .vco_shift = 20, .alpha_en_mask = BIT(24), .output_mask = 0xF, }; static struct alpha_pll_vco_tbl alpha_pll_vco_20nm_p[] = { Loading @@ -693,6 +694,7 @@ static struct alpha_pll_clk cci_pll = { .base = &vbases[CCI_PLL_BASE], .vco_tbl = alpha_pll_vco_20nm_p, .num_vco = ARRAY_SIZE(alpha_pll_vco_20nm_p), .enable_config = 0x9, /* Main and early outputs */ .c = { .parent = &xo_ao.c, .dbg_name = "cci_pll", Loading