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Commit 565e95b0 authored by Shrenuj Bansal's avatar Shrenuj Bansal
Browse files

msm: kgsl: Add RECORD_PFP_TIMESTAMP packet 



Use the RECORD_PFP_TIMESTAMP packet to read RBBM's ALWAYSON_COUNTER
and write it to a memory location instead of using the REG_TO_MEM
packet which would require more ordinals.

Change-Id: Ie2d29a75ecb75c9f25a4fba34ef4d71ab61bfa75
Signed-off-by: default avatarShrenuj Bansal <shrenujb@codeaurora.org>
parent f4dcba2b

drivers/gpu/msm/adreno.h

+0 −1
Original line number Diff line number Diff line
@@ -445,7 +445,6 @@ enum adreno_regs { 
	ADRENO_REG_UCHE_INVALIDATE0,

	ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_LO,

	ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_HI,

	ADRENO_REG_RBBM_ALWAYSON_COUNTER_LO,

	ADRENO_REG_REGISTER_MAX,

};

drivers/gpu/msm/adreno_a4xx.c

+0 −2
Original line number Diff line number Diff line
@@ -844,8 +844,6 @@ static unsigned int a4xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
				A4XX_RBBM_PERFCTR_LOAD_VALUE_LO),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_HI,

				A4XX_RBBM_PERFCTR_LOAD_VALUE_HI),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_ALWAYSON_COUNTER_LO,

				A4XX_RBBM_ALWAYSON_COUNTER_LO),

};



const struct adreno_reg_offsets a4xx_reg_offsets = {

drivers/gpu/msm/adreno_pm4types.h

+3 −0
Original line number Diff line number Diff line
@@ -163,6 +163,9 @@ 
/* PFP waits until the FIFO between the PFP and the ME is empty */

#define CP_WAIT_FOR_ME		0x13



/* Record the real-time when this packet is processed by PFP */

#define CP_RECORD_PFP_TIMESTAMP	0x11



/*

 * for a20x

 * program an offset that will added to the BIN_BASE value of

drivers/gpu/msm/adreno_ringbuffer.c

+2 −8
Original line number Diff line number Diff line
@@ -1318,10 +1318,7 @@ int adreno_ringbuffer_submitcmd(struct adreno_device *adreno_dev, 
	 * write it into the appropriate cmdbatch profiling buffer offset

	 */

	if (cmdbatch_profiling) {

		*cmds++ = cp_type3_packet(CP_REG_TO_MEM, 2);

		*cmds++ = adreno_getreg(adreno_dev,

				ADRENO_REG_RBBM_ALWAYSON_COUNTER_LO) |

				(1 << 30) | (2 << 18);

		*cmds++ = cp_type3_packet(CP_RECORD_PFP_TIMESTAMP, 1);

		*cmds++ = cmdbatch->profiling_buffer_gpuaddr +

				offsetof(struct kgsl_cmdbatch_profiling_buffer,

				gpu_ticks_submitted);
@@ -1353,10 +1350,7 @@ int adreno_ringbuffer_submitcmd(struct adreno_device *adreno_dev, 
	 * write it into the appropriate cmdbatch profiling buffer offset

	 */

	if (cmdbatch_profiling) {

		*cmds++ = cp_type3_packet(CP_REG_TO_MEM, 2);

		*cmds++ = adreno_getreg(adreno_dev,

				ADRENO_REG_RBBM_ALWAYSON_COUNTER_LO) |

				(1 << 30) | (2 << 18);

		*cmds++ = cp_type3_packet(CP_RECORD_PFP_TIMESTAMP, 1);

		*cmds++ = cmdbatch->profiling_buffer_gpuaddr +

				offsetof(struct kgsl_cmdbatch_profiling_buffer,

				gpu_ticks_retired);