Loading drivers/gpu/msm/adreno_ringbuffer.c +2 −0 Original line number Diff line number Diff line Loading @@ -1158,6 +1158,8 @@ void adreno_ringbuffer_set_constraint(struct kgsl_device *device, pwrlevel.level = constraint; } device->pwrctrl.constraint.expires = jiffies + device->pwrctrl.interval_timeout; } } Loading drivers/gpu/msm/kgsl_pwrctrl.c +5 −1 Original line number Diff line number Diff line Loading @@ -1504,12 +1504,16 @@ void kgsl_pwrctrl_enable(struct kgsl_device *device) int level; /* Order pwrrail/clk sequence based upon platform */ kgsl_pwrctrl_pwrrail(device, KGSL_PWRFLAGS_ON); if (pwr->wakeup_maxpwrlevel) { level = pwr->max_pwrlevel; pwr->wakeup_maxpwrlevel = 0; } else level = pwr->default_pwrlevel; if (pwr->constraint.type == KGSL_CONSTRAINT_NONE) kgsl_pwrctrl_pwrlevel_change(device, level); kgsl_pwrctrl_clk(device, KGSL_PWRFLAGS_ON, KGSL_STATE_ACTIVE); kgsl_pwrctrl_axi(device, KGSL_PWRFLAGS_ON); } Loading drivers/gpu/msm/kgsl_pwrctrl.h +1 −0 Original line number Diff line number Diff line Loading @@ -51,6 +51,7 @@ struct kgsl_pwr_constraint { unsigned int level; } pwrlevel; } hint; unsigned long expires; }; /** Loading drivers/gpu/msm/kgsl_pwrscale.c +19 −6 Original line number Diff line number Diff line Loading @@ -235,12 +235,25 @@ int kgsl_devfreq_target(struct device *dev, unsigned long *freq, u32 flags) kgsl_pwrctrl_buslevel_update(device, true); } /* * The power constraints need an entire interval to do their magic, so * skip changing the powerlevel if the time hasn't expired yet and the * new level is less than the constraint */ if ((pwr->constraint.type != KGSL_CONSTRAINT_NONE) && (!time_after(jiffies, pwr->constraint.expires)) && (level >= pwr->constraint.hint.pwrlevel.level)) *freq = cur_freq; else { /* Change the power level */ kgsl_pwrctrl_pwrlevel_change(device, level); /*Invalidate the constraint set */ pwr->constraint.type = KGSL_CONSTRAINT_NONE; pwr->constraint.expires = 0; *freq = kgsl_pwrctrl_active_freq(pwr); } mutex_unlock(&device->mutex); return 0; Loading Loading
drivers/gpu/msm/adreno_ringbuffer.c +2 −0 Original line number Diff line number Diff line Loading @@ -1158,6 +1158,8 @@ void adreno_ringbuffer_set_constraint(struct kgsl_device *device, pwrlevel.level = constraint; } device->pwrctrl.constraint.expires = jiffies + device->pwrctrl.interval_timeout; } } Loading
drivers/gpu/msm/kgsl_pwrctrl.c +5 −1 Original line number Diff line number Diff line Loading @@ -1504,12 +1504,16 @@ void kgsl_pwrctrl_enable(struct kgsl_device *device) int level; /* Order pwrrail/clk sequence based upon platform */ kgsl_pwrctrl_pwrrail(device, KGSL_PWRFLAGS_ON); if (pwr->wakeup_maxpwrlevel) { level = pwr->max_pwrlevel; pwr->wakeup_maxpwrlevel = 0; } else level = pwr->default_pwrlevel; if (pwr->constraint.type == KGSL_CONSTRAINT_NONE) kgsl_pwrctrl_pwrlevel_change(device, level); kgsl_pwrctrl_clk(device, KGSL_PWRFLAGS_ON, KGSL_STATE_ACTIVE); kgsl_pwrctrl_axi(device, KGSL_PWRFLAGS_ON); } Loading
drivers/gpu/msm/kgsl_pwrctrl.h +1 −0 Original line number Diff line number Diff line Loading @@ -51,6 +51,7 @@ struct kgsl_pwr_constraint { unsigned int level; } pwrlevel; } hint; unsigned long expires; }; /** Loading
drivers/gpu/msm/kgsl_pwrscale.c +19 −6 Original line number Diff line number Diff line Loading @@ -235,12 +235,25 @@ int kgsl_devfreq_target(struct device *dev, unsigned long *freq, u32 flags) kgsl_pwrctrl_buslevel_update(device, true); } /* * The power constraints need an entire interval to do their magic, so * skip changing the powerlevel if the time hasn't expired yet and the * new level is less than the constraint */ if ((pwr->constraint.type != KGSL_CONSTRAINT_NONE) && (!time_after(jiffies, pwr->constraint.expires)) && (level >= pwr->constraint.hint.pwrlevel.level)) *freq = cur_freq; else { /* Change the power level */ kgsl_pwrctrl_pwrlevel_change(device, level); /*Invalidate the constraint set */ pwr->constraint.type = KGSL_CONSTRAINT_NONE; pwr->constraint.expires = 0; *freq = kgsl_pwrctrl_active_freq(pwr); } mutex_unlock(&device->mutex); return 0; Loading