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Commit 5515dbc7 authored by Praveen Chidambaram's avatar Praveen Chidambaram Committed by Archana Sathyakumar
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msm: spm: Update msm_spm_turn_on_cpu_rail() to use new SAW2 base address 



Update the msm_spm_turn_on_cpu_rail() to use SAW2 base addresses passed
from the release_secondary to turn on the cpu rail, before bringing back
the cpu online.

Change-Id: Ic57d3995c42291d9d2f28f03591823056bf0ff41
Signed-off-by: default avatarPraveen Chidambaram <pchidamb@codeaurora.org>
parent 61d15c3a

arch/arm/mach-msm/platsmp.c

+2 −2
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ 
#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0

#define SCSS_CPU1CORE_RESET 0xD80

#define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64



#define MSM8960_SAW2_BASE_ADDR 0x02089000

/*

 * Write pen_release in a way that is guaranteed to be visible to all

 * observers, irrespective of whether they're taking part in coherency
@@ -104,7 +104,7 @@ static int __cpuinit msm8960_release_secondary(unsigned long base, 
	if (!base_ptr)

		return -ENODEV;



	msm_spm_turn_on_cpu_rail(cpu);

	msm_spm_turn_on_cpu_rail(MSM8960_SAW2_BASE_ADDR, cpu);



	writel_relaxed(0x109, base_ptr+0x04);

	writel_relaxed(0x101, base_ptr+0x04);

arch/arm/mach-msm/spm.h

+2 −9
Original line number Diff line number Diff line
@@ -130,14 +130,7 @@ struct msm_spm_platform_data { 
int msm_spm_set_low_power_mode(unsigned int mode, bool notify_rpm);

int msm_spm_set_vdd(unsigned int cpu, unsigned int vlevel);

unsigned int msm_spm_get_vdd(unsigned int cpu);

#if defined(CONFIG_MSM_SPM_V2)

int msm_spm_turn_on_cpu_rail(unsigned int cpu);

#else

static inline int msm_spm_turn_on_cpu_rail(unsigned int cpu)

{

	return -ENOSYS;

}

#endif

int msm_spm_turn_on_cpu_rail(unsigned long base, unsigned int cpu);



/* Internal low power management specific functions */
@@ -207,7 +200,7 @@ static inline void msm_spm_reinit(void) 
	/* empty */

}



static inline int msm_spm_turn_on_cpu_rail(unsigned int cpu)

static inline int msm_spm_turn_on_cpu_rail(unsigned long base, unsigned int cpu)

{

	return -ENOSYS;

}

arch/arm/mach-msm/spm_devices.c

+20 −17
Original line number Diff line number Diff line
@@ -203,38 +203,41 @@ spm_failed_malloc: 


/**

 * msm_spm_turn_on_cpu_rail(): Power on cpu rail before turning on core

 * @base: core 0's base SAW address

 * @cpu: core id

 */

int msm_spm_turn_on_cpu_rail(unsigned int cpu)

int msm_spm_turn_on_cpu_rail(unsigned long base, unsigned int cpu)

{

	uint32_t val = 0;

	uint32_t timeout = 0;

	uint32_t timeout = 512; /* delay for voltage to settle on the core */

	void *reg = NULL;

	void *saw_bases[] = {

		0,

		MSM_SAW1_BASE,

		MSM_SAW2_BASE,

		MSM_SAW3_BASE

	};



	if (cpu == 0 || cpu >= num_possible_cpus())

		return -EINVAL;



	reg = saw_bases[cpu];

	reg = ioremap_nocache(base + (cpu * 0x10000), SZ_4K);

	if (!reg)

		return -ENOMEM;



	if (soc_class_is_msm8960() || soc_class_is_msm8930() ||

	    soc_class_is_apq8064()) {

		val = 0xA4;

		reg += 0x14;

		timeout = 512;

	} else {

		return -ENOSYS;

	}

	reg += 0x1C;



	/*

	 * Set FTS2 type CPU supply regulator to 1.15 V. This assumes that the

	 * regulator is already configured in LV range.

	 */

	val = 0x40000E6;

	writel_relaxed(val, reg);

	mb();

	udelay(timeout);



	/* Enable CPU supply regulator */

	val = 0x2030080;

	writel_relaxed(val, reg);

	mb();

	udelay(timeout);



	iounmap(reg);



	return 0;

}

EXPORT_SYMBOL(msm_spm_turn_on_cpu_rail);