Merge "ARM: dts: Document the CCI PMU DT bindings"

				    corresponding interface programming

				    registers.

	- CCI PMU node

		Parent node must be CCI interconnect node.

		A CCI pmu node must contain the following properties:

		- compatible

			Usage: required

			Value type: <string>

			Definition: must be "arm,cci-400-pmu"

		- reg:

			Usage: required

			Value type: Integer cells. A register entry, expressed

				    as a pair of cells, containing base and

				    size.

			Definition: the base address and size of the

				    corresponding interface programming

				    registers.

		- interrupts:

			Usage: required

			Value type: Integer cells. Array of interrupt specifier

				    entries, as defined in

				    ../interrupt-controller/interrupts.txt.

			Definition: list of counter overflow interrupts, one per

				    counter. The interrupts must be specified

				    starting with the cycle counter overflow

				    interrupt, followed by counter0 overflow

				    interrupt, counter1 overflow interrupt,...

				    ,counterN overflow interrupt.

				    The CCI PMU has an interrupt signal for each

				    counter. The number of interrupts must be

				    equal to the number of counters.

* CCI interconnect bus masters

	Description: masters in the device tree connected to a CCI port

		#address-cells = <1>;

		#size-cells = <1>;

		reg = <0x0 0x2c090000 0 0x1000>;

		ranges = <0x0 0x0 0x2c090000 0x6000>;

		ranges = <0x0 0x0 0x2c090000 0x10000>;

		cci_control0: slave-if@1000 {

			compatible = "arm,cci-400-ctrl-if";

			interface-type = "ace";

			reg = <0x5000 0x1000>;

		};

		pmu@9000 {

			 compatible = "arm,cci-400-pmu";

			 reg = <0x9000 0x5000>;

			 interrupts = <0 101 4>,

				      <0 102 4>,

				      <0 103 4>,

				      <0 104 4>,

				      <0 105 4>;

		};

	};

This CCI node corresponds to a CCI component whose control registers sits