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Commit 53e061d9 authored by Jack Pham's avatar Jack Pham
Browse files

ARM: dts: msm: Enable USB BAM on APQ8084 



Enable USB BAM device for the SS USB core, which allows for
BAM-enabled USB transfers for functions such as QDSS. Also
fix the following:

- the FIFO base address should be specified as a 32-bit value
- the data FIFO offset to the USB3 controller's internal memory
  was pointing to the wrong address
- add TX FIFO size parameters specifying the available memory in
  the USB3 controller both when QDSS is enabled and disabled

Change-Id: I35eee4c4c2d747aad9b9f25b4005cc3e3cb1c477
Signed-off-by: default avatarJack Pham <jackp@codeaurora.org>
parent bb10e08c

arch/arm/boot/dts/apq8084.dtsi

+3 −2
Original line number Diff line number Diff line
@@ -1308,7 +1308,6 @@ 
	};



	qcom,usbbam@f9304000 {

		status = "disabled";

		compatible = "qcom,usb-bam-msm";

		reg = <0xf9304000 0x5000>,

		      <0xf92f880c 0x4>;
@@ -1316,7 +1315,7 @@ 
		interrupts = <0 132 0>;

		interrupt-names = "ssusb";

		qcom,usb-bam-num-pipes = <16>;

		qcom,usb-bam-fifo-baseaddr = <0x00000000 0xf9200000>;

		qcom,usb-bam-fifo-baseaddr = <0xf9200000>;

		qcom,ignore-core-reset-ack;

		qcom,disable-clk-gating;
@@ -1380,6 +1379,8 @@ 


		USB3_GDSC-supply = <&gdsc_usb30>;

		qcom,dwc-usb3-msm-dbm-eps = <4>;

		qcom,dwc-usb3-msm-tx-fifo-size = <29696>;

		qcom,dwc-usb3-msm-qdss-tx-fifo-size = <8192>;

		qcom,otg-capability;

		qcom,misc-ref = <&pma8084_misc>;

		qcom,restore-sec-cfg-for-scm-dev-id = <9>;