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Commit 53d9399e authored by Naveen Kaje's avatar Naveen Kaje
Browse files

ARM: dts: msm: Enable HSUART node for msmzirc 



Configure one BLSP HSUART node for BT enablement.

Change-Id: I93359fdbceb67ffcf1972567fe005c666c5fa80c
Signed-off-by: default avatarNaveen Kaje <nkaje@codeaurora.org>
parent 0b5fe757

arch/arm/boot/dts/qcom/msmzirc-cdp.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -28,6 +28,10 @@ 
	pinctrl-0 = <&uart3_console_active>;

};



&blsp1_uart2 {

	status = "ok";

};



&spi_1 {

	status = "ok";

	ethernet-switch@0 {

arch/arm/boot/dts/qcom/msmzirc-mtp.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -32,6 +32,10 @@ 
	pinctrl-0 = <&uart3_console_active>;

};



&blsp1_uart2 {

	status = "ok";

};



&spi_1 {

	status = "ok";

	ethernet-switch@0 {

arch/arm/boot/dts/qcom/msmzirc-pinctrl.dtsi

+22 −0
Original line number Diff line number Diff line
@@ -54,6 +54,28 @@ 
			};

		};



		blsp1_uart2_active {

			qcom,pins = <&gp 4>, <&gp 5>, <&gp 6>, <&gp 7>;

			qcom,num-grp-pins = <4>;

			qcom,pin-func = <2>;

		        label = "blsp1_uart2_active";

			hsuart_active: default {

				drive-strength = <16>;

				bias-disable;

			};

		};



		blsp1_uart2_sleep {

			qcom,pins = <&gp 4>, <&gp 5>, <&gp 6>, <&gp 7>;

			qcom,num-grp-pins = <4>;

			qcom,pin-func = <0>;

		        label = "blsp1_uart2_sleep";

			hsuart_sleep: sleep {

				drive-strength = <2>;

				bias-disable;

			};

		};



		spi0_active {

			/* MOSI, MISO, CLK */

			qcom,pins = <&gp 0>, <&gp 1>, <&gp 3>;

arch/arm/boot/dts/qcom/msmzirc.dtsi

+37 −10
Original line number Diff line number Diff line
@@ -233,16 +233,6 @@ 
		status = "disabled";

	};



	blsp1_uart2: serial@78b0000 {

		compatible = "qcom,msm-lsuart-v14";

		reg = <0x78b0000 0x200>;

		interrupts = <0 108 0>;

		clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,

			 <&clock_gcc clk_gcc_blsp1_ahb_clk>;

		clock-names = "core_clk", "iface_clk";

		status = "disabled";

	};



	blsp1_uart3: serial@78b1000 {

		compatible = "qcom,msm-lsuart-v14";

		reg = <0x78b1000 0x200>;
@@ -253,6 +243,43 @@ 
		status = "disabled";

	};



	blsp1_uart2: uart@0x78b0000 { /* BLSP1 UART2 */

		compatible = "qcom,msm-hsuart-v14";

		reg = <0x78b0000 0x200>,

		      <0x7884000 0x23000>;

		reg-names = "core_mem", "bam_mem";

		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";

		#address-cells = <0>;

		interrupt-parent = <&blsp1_uart2>;

		interrupts = <0 1 2>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0xffffffff>;

		interrupt-map = <0 &intc 0 108 0

				1 &intc 0 238 0

				2 &msm_gpio 5 0>;



		qcom,inject-rx-on-wakeup;

		qcom,rx-char-to-inject = <0xFD>;



		qcom,bam-tx-ep-pipe-index = <2>;

		qcom,bam-rx-ep-pipe-index = <3>;

		qcom,master-id = <86>;

		clock-names = "core_clk", "iface_clk";

		clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,

			<&clock_gcc clk_gcc_blsp1_ahb_clk>;

		pinctrl-names = "sleep", "default";

		pinctrl-0 = <&hsuart_sleep>;

		pinctrl-1 = <&hsuart_active>;



		qcom,msm-bus,name = "buart2";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<86 512 0 0>,

				<86 512 500 800>;

		status = "disabled";

	};



	qcom,sps {

		compatible = "qcom,msm_sps_4k";

		qcom,device-type = <3>;