Loading arch/arm/boot/dts/qcom/msm8994.dtsi +56 −0 Original line number Diff line number Diff line Loading @@ -80,6 +80,7 @@ reg = <0x0>; enable-method = "qcom,8994-arm-cortex-acc"; qcom,acc = <&acc0>; qcom,ldo = <&ldo0>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "arm,arch-cache"; Loading @@ -106,6 +107,7 @@ reg = <0x1>; enable-method = "qcom,8994-arm-cortex-acc"; qcom,acc = <&acc1>; qcom,ldo = <&ldo1>; next-level-cache = <&L2_0>; L1_I_1: l1-icache { compatible = "arm,arch-cache"; Loading @@ -123,6 +125,7 @@ reg = <0x2>; enable-method = "qcom,8994-arm-cortex-acc"; qcom,acc = <&acc2>; qcom,ldo = <&ldo2>; next-level-cache = <&L2_0>; L1_I_2: l1-icache { compatible = "arm,arch-cache"; Loading @@ -140,6 +143,7 @@ reg = <0x3>; enable-method = "qcom,8994-arm-cortex-acc"; qcom,acc = <&acc3>; qcom,ldo = <&ldo3>; next-level-cache = <&L2_0>; L1_I_3: l1-icache { compatible = "arm,arch-cache"; Loading @@ -157,6 +161,7 @@ reg = <0x100>; enable-method = "qcom,8994-arm-cortex-acc"; qcom,acc = <&acc4>; qcom,ldo = <&ldo4>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "arm,arch-cache"; Loading Loading @@ -189,6 +194,7 @@ reg = <0x101>; enable-method = "qcom,8994-arm-cortex-acc"; qcom,acc = <&acc5>; qcom,ldo = <&ldo5>; next-level-cache = <&L2_1>; L1_itlb_101: l1-itlb { qcom,dump-size = <0x400>; Loading @@ -212,6 +218,7 @@ reg = <0x102>; enable-method = "qcom,8994-arm-cortex-acc"; qcom,acc = <&acc6>; qcom,ldo = <&ldo6>; next-level-cache = <&L2_1>; L1_itlb_102: l1-itlb { qcom,dump-size = <0x400>; Loading @@ -235,6 +242,7 @@ reg = <0x103>; enable-method = "qcom,8994-arm-cortex-acc"; qcom,acc = <&acc7>; qcom,ldo = <&ldo7>; next-level-cache = <&L2_1>; L1_itlb_103: l1-itlb { qcom,dump-size = <0x400>; Loading Loading @@ -391,6 +399,54 @@ <0xf900b000 0x1000>; }; ldo0:ldo-vref@f9070000 { compatible = "qcom,8994-cpu-ldo-vref"; reg = <0xf9070000 0x30>; qcom,ldo-vref-ret = <0x3e>; }; ldo1:ldo-vref@f9071000 { compatible = "qcom,8994-cpu-ldo-vref"; reg = <0xf9071000 0x30>; qcom,ldo-vref-ret = <0x3e>; }; ldo2:ldo-vref@f9072000 { compatible = "qcom,8994-cpu-ldo-vref"; reg = <0xf9072000 0x30>; qcom,ldo-vref-ret = <0x3e>; }; ldo3:ldo-vref@f9073000 { compatible = "qcom,8994-cpu-ldo-vref"; reg = <0xf9073000 0x30>; qcom,ldo-vref-ret = <0x3e>; }; ldo4:ldo-vref@f9074000 { compatible = "qcom,8994-cpu-ldo-vref"; reg = <0xf9074000 0x30>; qcom,ldo-vref-ret = <0x3e>; }; ldo5:ldo-vref@f9075000 { compatible = "qcom,8994-cpu-ldo-vref"; reg = <0xf9075000 0x30>; qcom,ldo-vref-ret = <0x3e>; }; ldo6:ldo-vref@f9076000 { compatible = "qcom,8994-cpu-ldo-vref"; reg = <0xf9076000 0x30>; qcom,ldo-vref-ret = <0x3e>; }; ldo7:ldo-vref@f9077000 { compatible = "qcom,8994-cpu-ldo-vref"; reg = <0xf9077000 0x30>; qcom,ldo-vref-ret = <0x3e>; }; l2ccc_0: clock-controller@f900d000 { compatible = "qcom,8994-l2ccc"; reg = <0xf900d000 0x1000>, Loading Loading
arch/arm/boot/dts/qcom/msm8994.dtsi +56 −0 Original line number Diff line number Diff line Loading @@ -80,6 +80,7 @@ reg = <0x0>; enable-method = "qcom,8994-arm-cortex-acc"; qcom,acc = <&acc0>; qcom,ldo = <&ldo0>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "arm,arch-cache"; Loading @@ -106,6 +107,7 @@ reg = <0x1>; enable-method = "qcom,8994-arm-cortex-acc"; qcom,acc = <&acc1>; qcom,ldo = <&ldo1>; next-level-cache = <&L2_0>; L1_I_1: l1-icache { compatible = "arm,arch-cache"; Loading @@ -123,6 +125,7 @@ reg = <0x2>; enable-method = "qcom,8994-arm-cortex-acc"; qcom,acc = <&acc2>; qcom,ldo = <&ldo2>; next-level-cache = <&L2_0>; L1_I_2: l1-icache { compatible = "arm,arch-cache"; Loading @@ -140,6 +143,7 @@ reg = <0x3>; enable-method = "qcom,8994-arm-cortex-acc"; qcom,acc = <&acc3>; qcom,ldo = <&ldo3>; next-level-cache = <&L2_0>; L1_I_3: l1-icache { compatible = "arm,arch-cache"; Loading @@ -157,6 +161,7 @@ reg = <0x100>; enable-method = "qcom,8994-arm-cortex-acc"; qcom,acc = <&acc4>; qcom,ldo = <&ldo4>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "arm,arch-cache"; Loading Loading @@ -189,6 +194,7 @@ reg = <0x101>; enable-method = "qcom,8994-arm-cortex-acc"; qcom,acc = <&acc5>; qcom,ldo = <&ldo5>; next-level-cache = <&L2_1>; L1_itlb_101: l1-itlb { qcom,dump-size = <0x400>; Loading @@ -212,6 +218,7 @@ reg = <0x102>; enable-method = "qcom,8994-arm-cortex-acc"; qcom,acc = <&acc6>; qcom,ldo = <&ldo6>; next-level-cache = <&L2_1>; L1_itlb_102: l1-itlb { qcom,dump-size = <0x400>; Loading @@ -235,6 +242,7 @@ reg = <0x103>; enable-method = "qcom,8994-arm-cortex-acc"; qcom,acc = <&acc7>; qcom,ldo = <&ldo7>; next-level-cache = <&L2_1>; L1_itlb_103: l1-itlb { qcom,dump-size = <0x400>; Loading Loading @@ -391,6 +399,54 @@ <0xf900b000 0x1000>; }; ldo0:ldo-vref@f9070000 { compatible = "qcom,8994-cpu-ldo-vref"; reg = <0xf9070000 0x30>; qcom,ldo-vref-ret = <0x3e>; }; ldo1:ldo-vref@f9071000 { compatible = "qcom,8994-cpu-ldo-vref"; reg = <0xf9071000 0x30>; qcom,ldo-vref-ret = <0x3e>; }; ldo2:ldo-vref@f9072000 { compatible = "qcom,8994-cpu-ldo-vref"; reg = <0xf9072000 0x30>; qcom,ldo-vref-ret = <0x3e>; }; ldo3:ldo-vref@f9073000 { compatible = "qcom,8994-cpu-ldo-vref"; reg = <0xf9073000 0x30>; qcom,ldo-vref-ret = <0x3e>; }; ldo4:ldo-vref@f9074000 { compatible = "qcom,8994-cpu-ldo-vref"; reg = <0xf9074000 0x30>; qcom,ldo-vref-ret = <0x3e>; }; ldo5:ldo-vref@f9075000 { compatible = "qcom,8994-cpu-ldo-vref"; reg = <0xf9075000 0x30>; qcom,ldo-vref-ret = <0x3e>; }; ldo6:ldo-vref@f9076000 { compatible = "qcom,8994-cpu-ldo-vref"; reg = <0xf9076000 0x30>; qcom,ldo-vref-ret = <0x3e>; }; ldo7:ldo-vref@f9077000 { compatible = "qcom,8994-cpu-ldo-vref"; reg = <0xf9077000 0x30>; qcom,ldo-vref-ret = <0x3e>; }; l2ccc_0: clock-controller@f900d000 { compatible = "qcom,8994-l2ccc"; reg = <0xf900d000 0x1000>, Loading